Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-07-12
2011-07-12
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S755000, C714S786000
Reexamination Certificate
active
07979780
ABSTRACT:
An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block1, (n−1)-th-order polynomial multiplying units (12-1to12-(m−1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m−1) blocks having a length n and a single block having a length (n−r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length. An r-th-order polynomial dividing unit2receives an addition of the outputs from the respective (n−1)-th-order polynomial multiplying units (12-1to12-(m−1)) and also receives a block having the length (n−r), and outputs a redundant bit series having a length r.
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Lamarre Guy J
NEC Corporation
Young & Thompson
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