Error correction coding/decoding method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

active

06581178

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an error correction coding/decoding method and apparatus.
Conventionally, in data transmission by a digital communication system or data storage by a digital storage device, error correction coding and decoding are performed to detect a data error from an error-correcting code (also called a redundant code) and correct the error to improve the reliability. As the error-correcting code, a multidimensional code such as a Hamming code, BCH (Bose-Chaudhuri-Hocquenghem) code, or Reed-Solomon code is known. The multidimensional code is originally has a plurality of bits, and allows correct burst error correction or byte error correction.
FIG. 20
shows the arrangement of a conventional error correction coding/decoding apparatus. In an error correction coding/decoding apparatus
2000
, a horizontal line block in transmission data is subjected to error correction coding by a horizontal line block error correction coding circuit
2011
of an error correction encoder
2010
and output (transmission data). Reception data is input to a horizontal line block error correction decoding circuit
2021
of an error correction decoder
2020
, subjected to error correction decoding for a horizontal line block, and then output (decoded data).
In error correction by horizontal line block coding for a BCH code which allows 2-bit error correction, if a horizontal line block has errors in number larger than 2 bits, the errors cannot be corrected. For example, when information bits (49 bits) are represented using a BCH code capable of 2-bit error correction, and a given coded block (coded block
1
) has errors of 3 bits or more, as shown in Table 1, the errors cannot be corrected.
TABLE 1
Coded Block Number
Information Bits (49 bits) Check Bits (56 bits)
Coded Block 1
XXX◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 2
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 3
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 4
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 5
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 6
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
Coded Block 7
◯◯◯◯◯◯◯ + ◯◯◯◯◯◯◯◯
For such error correction processing, various proposals for improvement have been made. For example, Japanese Patent Laid-Open No. 5-235906 discloses a “decoder for multidimensional code and error correction detection system using decoder” in which in decoding a multidimensional code, the highest bit likelihood in a symbol is used as the largest length to eliminate an error symbol at a high probability.
Japanese Patent Laid-Open No. 5-347564 discloses an error correction coding/decoding method and device and error correction decoding device using error correction using a block code. In this case, a punctured code is used at a coding rate higher than that of an original code, and high system compatibility is obtained.
Japanese Patent Publication No. 7-99503 discloses an “error correction method for coded data” in which for data subjected to triple error correction coding, error correction using a second code is reduced, and the correction ability for the third code is improved to obtain a higher correction ability even when a burst error is mixed.
However, in these prior arts, for, e.g., a BCH code capable of 2-bit error correction, if errors of 3 bits or more are present in a horizontal line block, the errors cannot be corrected.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problems of prior arts, and has as its object to enable correction of an error pattern that cannot be corrected by a conventional arrangement. It is another object of the present invention to improve the error correction probability and allow high-speed decoding processing.
In order to achieve the above object, according to an aspect of the present invention, there is provided an error correction coding method comprising segmenting continuous transmission data in units of predetermined lengths, rearranging the data parallelly, and performing error correction coding processing for each of horizontal line blocks and vertical line blocks of the rearranged transmission data.


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patent: 64-47132 (1989-02-01), None
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patent: 5-235906 (1993-09-01), None
patent: 5-347564 (1993-12-01), None
R.M. Pyndiah, “Near-Optimum Decoding of Product Codes: Block Turbo Codes”, IEEE Transactions on Communications, vol. 46, No. 8, (Aug. 1998), pp. 1003-1010.

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