Error correction coding apparatus and method

Details Error correction coding apparatus and method Error correction coding apparatus and method

2007-03-06

2007-03-06

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C714S801000, C714S804000, C714S755000

Reexamination Certificate

active

10680419

ABSTRACT:
An error correction coding apparatus includes a parity check matrix generation unit which generates a parity check matrix having a number of elements having a value of 1 in each row thereof, having a predetermined number of elements having a value of 1 in each column thereof, and having the other elements having a value of 0; a parity check matrix adjustment unit which receives the parity check matrix from the parity check matrix generation unit, searches the parity check matrix for a cycle forming group of four elements positioned at respective vertexes of a rectangle and having a value of 1, and when there is at least one cycle forming group, replaces the value of 1 of at least one element of the cycle forming group with the value 0 of another element, to output a adjusted parity check matrix without a cycle forming group therein; and an LDPC coding unit which receives the adjusted parity check matrix from the parity check matrix adjustment unit and receives an m-bit message word to perform LDPC coding.

REFERENCES:
patent: 6944803 (2005-09-01), Hunt
patent: 2002/0042899 (2002-04-01), Tzannes et al.
patent: 2003/0037298 (2003-02-01), Eleftheriou et al.
patent: 2005/0229088 (2005-10-01), Tzannes et al.
patent: 01/97387 (2001-12-01), None
patent: WO 01/97387 (2001-12-01), None
McGowan, J.A., et al., “Loop Removal From LDPC Codes”, Proc. IEEE Information Theory Workshop, ITW 2003, Paris, France, Mar. 31, 2003, pp. 230-233, XP010647444.
Matsumoto, W. et al., “Irregular low-density parity check code design based on Euclidean geometries”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Institute of Electronics Information and Comm. Eng. Tokyo, JP, vol. E86-A, No. 7, Jul. 2003, pp. 1820-1834, XP001174812 ISSN: 0916-8508.
Mackay, D. J. C.,: “Good error-correcting codes based on very sparse matrices” IEEE Transactions on Information Theory, IEEE Inc. New York, US, vol. 45, No. 2, Mar. 1999, pp. 399-431, XP002143042 ISSN: 0018-9448.
Davey, M. C., et al., “Low density parity check codes over GF(q)”, Proc. IEEE Information Theory Workshop, ITW 1998, Killarney, Ireland, Jun. 22-26, 1998, pp. 70-71, XP010297325 ISBN: 0-7803-4408-1
European Search Report dated Sep. 30, 2004.
Office Action issued in Japanese Patent Application No. 2003-352528 on Oct. 4, 2005.
Office Action issued on May 19, 2006, in Chinese Patent Application No. 200310120939.3 (in Chinese with English translation).

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