Error correction coding and decoding in a solid-state...

Details Error correction coding and decoding in a solid-state... Error correction coding and decoding in a solid-state...

2006-04-25

2006-04-25

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S746000

Reexamination Certificate

active

07036068

ABSTRACT:
A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells16of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols206in a block of ECC encoded data204which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells16. Where the position of suspected failed symbols206is known from this erasure information, the ability of a decoder22to perform ECC decoding is substantially enhanced.

REFERENCES:
patent: 4069970 (1978-01-01), Buzzard et al.
patent: 4209846 (1980-06-01), Seppa
patent: 4216541 (1980-08-01), Clover et al.
patent: 4458349 (1984-07-01), Aichelmann, Jr. et al.
patent: 4933940 (1990-06-01), Walter et al.
patent: 4939694 (1990-07-01), Eaton et al.
patent: 5459742 (1995-10-01), Cassidy et al.
patent: 5502728 (1996-03-01), Smith, III
patent: 5504760 (1996-04-01), Harari et al.
patent: 5745673 (1998-04-01), Di Zenzo et al.
patent: 5848076 (1998-12-01), Yoshimura
patent: 5852574 (1998-12-01), Naji
patent: 5887270 (1999-03-01), Brant et al.
patent: 5987573 (1999-11-01), Hiraka
patent: 6166944 (2000-12-01), Ogino
patent: 6279133 (2001-08-01), Vafai et al.
patent: 6430702 (2002-08-01), Santeler et al.
patent: 6456525 (2002-09-01), Perner et al.
patent: 2003/0023911 (2003-01-01), Davis et al.
patent: 2003/0023922 (2003-01-01), Davis et al.
patent: 2003/0023924 (2003-01-01), Davis et al.
patent: 2003/0023925 (2003-01-01), Davis et al.
patent: 2003/0023926 (2003-01-01), Davis et al.
patent: 2003/0023927 (2003-01-01), Jedwab et al.
patent: 2003/0023928 (2003-01-01), Jedwab et al.
patent: 2003/0172329 (2003-09-01), Davis et al.
patent: 2003/0172339 (2003-09-01), Davis et al.
patent: 0 494 547 (1992-07-01), None
patent: 0 918 334 (1999-05-01), None
patent: 1 132 924 (2000-10-01), None
Abstract of Japanese Patent No. JP 60007698, published Jan. 16, 1985, esp@cenet.com.
Peterson, W.W. and E.J. Weldon, Jr.,Error-Correcting Codes, Second Edition, MIT Press, Ch. 1-3, 8 and 9 (1994).
Reed-Solomon Codes and Their Applications, S.B. Wicker and V.K. Bhargava, ed., IEEE Press, New York, Ch. 1, 2, 4, and 12 (1994).

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