Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-03-07
2009-11-17
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07620875
ABSTRACT:
A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.
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Fallside Hamish T.
Nelson Michael D.
Abraham Esaw T
Maunu LeRoy D.
Xilinx , Inc.
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