Error correction code (ECC) decoding architecture design...

Details Error correction code (ECC) decoding architecture design... Error correction code (ECC) decoding architecture design...

2011-07-05

2011-07-05

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000, C714S758000

Reexamination Certificate

active

07975200

ABSTRACT:
Error correction code (ECC) decoding architecture design using synthesis-time design parameters. An approach is presented herein by which an ECC decoding architecture can be designed using synthesis-time design parameters. The manner presented herein allows for a designer to arrive at an ECC decoding architecture in a more direct, straightforward manner that using prior art means. A number of considerations (e.g., architecture parameters, semi-soft design constraints, parallel implementation, etc.) are initially provided; certain or all of these considerations can be predetermined, determined adaptively, and/or modified during the design process. A designer is provided a means by which a most desirable ECC decoding architecture can be arrived at relatively quickly.

REFERENCES:
patent: 6654916 (2003-11-01), Furukawa
patent: 2009/0177943 (2009-07-01), Silvus et al.

Affiliated with

Also associated with

Rating

Error correction code (ECC) decoding architecture design... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction code (ECC) decoding architecture design..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction code (ECC) decoding architecture design... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2728907