Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-07-09
2001-02-27
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06195781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Reed Solomon error correction code calculator for use with a digital video signal recording apparatus or the like.
2. Description of the Related Art
FIG. 1
shows an example of the structure of a conventional Reed Solomon error correction code calculator
110
. Unless an SW Cont signal is active (this state will be described later), switches
105
and
106
are placed in positions as shown in FIG.
1
. The Reed Solomon error correction code calculator
110
is initialized corresponding to the first one symbol (for example, one byte) of input data to be encoded. In other words, when the input data is supplied to the Reed Solomon error correction code calculator
110
, an initialization signal is supplied to selectors
104
1
to
104
n-1
. While the initialization signal is being supplied, the selectors
104
1
to
104
n-1
supply output signals of matrix calculators
100
1
to
100
n-1
to circuits on downstream stages, respectively. The selector
104
n
supplies
00
h
to an exclusive-OR gate (hereinafter referred to as EX-OR gate)
103
n
that performs an exclusive OR operation.
Thus, the initial input data is supplied as feedback data to the matrix calculators
100
1
to
100
n-1
. Calculated results of the initial input data are supplied to the registers
101
1
to
101
n-1
.
After such an initializing process is completed, the subsequent input data is supplied to the EX-OR gate
103
n
on the last stage. Output data of the register
104
n
on the last stage is supplied to the EX-OR gate
103
n
. The EX-OR gate
103
n
exclusive-ORs each of the second or later input data and output data of the register on the last stage and outputs the calculated result as feedback data.
In the initializing process and error correction code calculating process, input data to be encoded is supplied to a data processing means on a downstream stage through the switch
106
. Individual registers store parities to be added to input data to be encoded. When such processes are completed, the parities are added to the input data.
When the SW Cont signal becomes active, the switch
105
is placed in a position of which
00
h
(h represents hexadecimal notation) is supplied as feedback data. When
00
h
is supplied as feedback data to the matrix calculators
100
1
to
100
n-1
, the matrix calculators
100
1
to
100
n-1
, output
00
h
since, the matrix calculator
100
1
to
100
n-1
is composed with EX-OR gates. Thus, the EX-OR gates
103
1
to
103
n-1
(not EX-OR gate
103
n
on the last stage) that receive output data of the matrix calculators
100
1
to
100
n-1
and output data of the registers on the preceding stages always supply output data of the registers on the preceding stages to the registers on the next stages. In other words, in this case, the registers
101
1
to
101
n
structure a shift register.
When the SW Cont signal becomes active, the switch
106
is placed in a position of which output data of the register
104
n-1
on the last stage is supplied to a circuit on the next stage. Thus, parities to be added are successively output to circuits on the next stages. Thus, a corrected code is structured.
To add parities, a circuit structure of which output data of registers is selected by selectors may be used. To decrease the number of selectors and flexibly change the number of parities, conventionally, a circuit structure shown in
FIG. 1
is used.
To correct an error of digital data, a product code encoding method for encoding data with an inner code and an outer code has been widely used. When an error of pixel data is corrected, an outer code parity is added. Thereafter, to encode the resultant data with an inner code, the data array is converted and then an inner code parity is added. The resultant data array is recorded as it is.
When data is reproduced, an error thereof is corrected in the following manner. First, an error of the reproduced data is corrected with an inner code. Thereafter, to correct an error of the data with an outer code, the data array is converted and then the error of the data is corrected with an outer code. After the error of the data is corrected with the outer code, the data is restored to the original data array. Thus, the data array is converted twice in the recording operation and the reproducing operation.
When original data to be encoded has been compressed, each compressing unit of data (for example, each block) varies corresponding to the compressing method of the original data. Thus, adding processes of an inner code and an outer code and an error correcting process therewith become complicated.
When data is recorded with an error correction code, a data array is converted in the vertical direction. Thereafter, an outer code parity is added. Next, to encode the resultant data array with an inner code, the data array is converted in the horizontal direction. An inner code parity is added to each block of data. The resultant data is recorded in the inner code sequence.
When data is reproduced with an error correction code, an error of the reproduced data is corrected with an inner code. Thereafter, to correct an error of the data with an outer code, the data array is converted and then the resultant data is corrected with an outer code. In addition, the data array should be restored to the original data array. In the recording operation and reproducing operation, the data array is converted four times in total.
When original data has been compressed, the data array converting process should be performed twice as many as that of the normal pixel data. In addition, to convert the data array, two RAMs (Random Access Memories) each of which has a storage capacity for data of a product code should be disposed in the Reed Solomon error correction code calculator. In addition, the delay due to the data array converting process becomes twice as many as the length of the product code.
OBJECTS AND SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an error correction code calculator that encodes data with a product code without need to perform a data array converting process.
A first aspect of the present invention is a Reed Solomon error correction code calculator, comprising a plurality of modules, each of which has a memory, a matrix calculator, and an exclusive-OR circuit, the plurality of modules being cascade connected, and at least one register disposed between each of the plurality of modules.
A second aspect of the present invention is an error correction code calculator for encoding data with a product code for dually encoding each symbol, the product code being a Reed Solomon inner code and a Reed Solomon outer code, comprising a plurality of memories, each of which has a storage capacity for the number of symbols for an interleave length or equivalent thereto.
Thus, according to the present invention, an encoding process with a product code can be performed without need to convert a data array in the vertical and horizontal directions.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5392299 (1995-02-01), Rhines et al.
patent: 5696774 (1997-12-01), Inoue et al.
patent: 5729647 (1998-03-01), Kim
patent: 5887006 (1999-03-01), Sharma
Cady Albert De
Chang Dexter T.
Chase Shelly A
Frommer William S.
Frommer Lawrence & Haug LLP.
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