Error correction code block generating method and apparatus...

Details Error correction code block generating method and apparatus... Error correction code block generating method and apparatus...

2007-02-06

2007-02-06

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S766000

Reexamination Certificate

active

10335859

ABSTRACT:
An apparatus, method, and an optical storage medium to generate an error correction block include a data block generation unit processing digital data on a byte-by-byte basis and arranging the processed digital data from 0thto (N−1)thcolumns and from 0thto (M−1)throws to form (M×N) data blocks. A matrix block generation unit arranges the (M×N) data blocks in K rows according to a data transmission sequence to form a matrix block. A first codeword generation unit adds a first error correction check word of 2×K bytes to each of N columns to form a first codeword of ((K×M)+2×K) bytes. A second codeword generation unit adds a second error correction check word of P bytes to each of ((K×M)+2×K) rows to form a second codeword of (N+P) bytes.

REFERENCES:
patent: 6718510 (2004-04-01), Kojima
patent: 6910174 (2005-06-01), Keeler
patent: 2000-323996 (2000-11-01), None

Affiliated with

Also associated with

Rating

Error correction code block generating method and apparatus... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction code block generating method and apparatus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction code block generating method and apparatus... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3863141