Error correction circuit using a design based on a neural networ

Details Error correction circuit using a design based on a neural networ Error correction circuit using a design based on a neural networ

1990-07-09

1992-11-24

Beausoliel, Robert W.

Excavating

395 27, G06F 1108

Patent

active

051669382

ABSTRACT:
An error correction circuit is provided which uses NMOS and PMOS synapses to form network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.

REFERENCES:
patent: 4988891 (1991-01-01), Mashiko
patent: 5034918 (1991-07-01), Jeong
patent: 5047655 (1991-09-01), Chambost et al.
patent: 5058049 (1991-10-01), Anderson
Takefuji et al., Error Correcting System Based on Neural Circuits, IEEE catalog #87THO191-7, Jun. 1987.
Kwon et al., Implementation of a Programmable Artificial Neuron Using Discrete Logic, 1989 (no month available).
Eberhardt et al., Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI `Building Block` Chips, Jun. 1989.
Bloomer et al., A Preprogrammed Artificial Neural Network in Signal Processing, Proceedings of IEEE Custom IC May 1990.
Graf et al., VLSI Implementation of a Neural Network Model, 1988 (no month available).

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