Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-05-25
2004-04-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S776000
Reexamination Certificate
active
06728925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an error correcting method and an apparatus therefor, and in particular to a method and an apparatus for performing an error correction of a transmission signal with a Hamming code.
In a long distance transmission line of an optical transmission equipment by way of example, a loss caused by an optical fiber is compensated by the cascade connection of optical amplifiers, while a noise generated at each of the optical amplifiers deteriorates network quality parameters, e.g. a BER (Bit Error Rate).
As an efficient method to solve this problem, an error correcting method and an apparatus therefor are required by a transmitter making a message an error correcting code to be transmitted and a receiver detecting an error bit included in a received message to correct the bit.
2. Description of the Related Art
(1) It is known as a prior art error correcting method that for example, in “Design and Characterization of an Error-Correction Code for the SONET STS-1 Tributary” published in the IEEE TRANSACTIONS ON COMMUNICATION. VOL.38. NO.4 APRIL 1990, a Forward Error Correction (hereinafter occasionally abbreviated as FEC) is performed with a TOH portion (an SOH portion, an LOH portion) and a payload portion except the LOH portion within a single frame being allotted for an operation area by using a shortened Hamming code, and with Z
3
and Z
4
byte portions in a POH portion being allotted for check bits.
(2) Additionally, in “A forward error correcting scheme for SONET 10 Gb/s Optical Transmission system” published in the T1X1.5/94-148 July 12
th
1994 (ALCATEL NETWORK SYSTEM), the FEC is performed with the LOJ portion except the SOH portion and the payload portion within a single frame being allotted for the operation area by using the shortened Hamming code, with a single frame being divided into three, i.e. 9
th,
1
st,
2
nd
rows, 3
rd
-5
th
rows, and 6
th
-8
th
rows, with the check bits of the 9
th,
1
st
and 2
nd
rows being allotted for a D
3
byte portion of the SOH portion, with the check bits of the 3
rd
-5
th
rows being allotted for a D
6
byte portion of the LOU portion, and with the check bits of the 6
th-
8
th
rows being allotted for an E
2
byte portion of the LOH portion.
(3) Moreover, in “FORWARD ERROR CORRECTION FOR SUBMARINE SYSTEMS” published in the ITU-T (TELECOMMUNICATION STANDARDIZATION SECTION OF ITU) Recommendation G.975 (11/96), the FEC is performed with the whole of a single frame being allotted for the operation area by using an RS (Reed-Solomon) code, and with an increased part of a transmission speed being allotted for the check bits.
(4) Furthermore, in an error correcting/encoding method and a transmitter/receiver apparatus published in the Japanese Patent Publication Laid-open No.9-130355, the FEC is performed with the payload portion except the TOH portion within a single frame being allotted for the operation area by using the RS code, with a single frame being divided into two, and with non-defined byte portions in the LOH portion being allotted for the check bits.
By the error correcting method (1), since at least a single frame has to be held in a memory once, a transfer delay becomes 139 &mgr;seconds (=125 &mgr;seconds×900 bytes/810 bytes). This value does not satisfy the standard of transfer delay, i.e. equal to or less than 100 &mgr;seconds prescribed by ANSI T1.506A-1992, Telecommunication Performance-Specifications for Switched Exchange Network (Absolute, Round-trip Delay), ANSI T1.508-1992.
Also, by the error correcting method (2), since the SOH is used for the check bits and the SOH is terminated in case that a regenerator or relaying equipment is positioned on a transmission line, the FEC can not be performed.
Moreover, by the method (3), since the transmission speed is increased for the addition of the check bits, the apparatus executing this method is not based on the SONET and therefore an SDH is only used in an isolated state from the world standard.
Generally, what kind of error correcting codes can efficiently perform the error correction depends on an error occurrence pattern on a transmission equipment, a system, and a transmission line.
The error correcting methods (3) and (4) use the RS code. The RS code is suitable for the system where a burst error is generated. When the RS code is adopted for such a system, the BER is highly improved as compared with the case of the Hamming code.
However, the RS code requires a memory on the transmitter side and enlarges a circuit scale. Furthermore, assuming that the number of bits in one character is “n”, the RS code notifies that the number of errors is “1” in case the number of error bits is any one of 1 to n. Accordingly, the RS code can not accurately count the number of error bits.
Moreover, by the method (4), the transmission speed is an integer times of 622.08 Mb/s. In this case, compared with the case using the Hamming code, the higher the transmission speed, the larger the difference of both circuit scales.
In an optical transmission equipment or the like, it is required that the deterioration of BER by an optical amplifier is prevented and the frequency of switchover by an SD (Signal Degrade: a random error of 1×10
−2
−10
−9
rate) is decreased.
Generally, the Hamming code is suitable for a random error correction, and can accurately notify the number of corrected bits. The circuit scale for the Hamming code is smaller compared with that for the RS code since on the transmitter side of the CRC operation of information bits is performed and the result only has to be inserted into the check bits, eliminating any need of memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an error correcting method and an apparatus therefor using a Hamming code wherein the transfer delay is reduced, the BER is improved, and the circuit is small-scaled.
In order to achieve the above-mentioned object, an error correcting method according to the claim 1 divides a frame prescribed for a synchronous network into L Hamming code blocks, where L is a natural number≦9, in a direction of row and allots information bits and check bits to each of the blocks.
Namely, the Hamming code is required to temporarily hold all of the information on a receiver side when an error correction is performed. The transfer delay is caused for the holding time. By dividing a single frame into L Hamming code blocks and making the size of a single Hamming code block 1/L of a single frame, the transfer delay is reduced.
In the present invention according to the claim
2
, the synchronous network may comprise SONET or SDH, and the frame may comprise an STS-N frame, an OC-N frame, or an STM-N frame.
Namely, the synchronous network may be either the SONET or the SDH, and the frame may adopt either the STS-N frame or the OC-N frame prescribed by the SONET, or may adopt the STM-N frame prescribed by the SDH.
In the present invention according to the claim
3
, the information bits and the check bits may be allotted to a payload portion of the frame and non-defined bits of an LOH portion, respectively.
Namely, the information bits are allotted to the payload portion, while they are not allotted to the SOH portion and the LOH portion including B
1
and B
2
byte portions which have a possibility of being rewritten during transmission. The check bits are allotted to the non-defined bits of the LOH portion, while they are not allotted to the SOH portion terminated in a relaying equipment. Accordingly, an FEC can be performed without the Hamming code blocks being rewritten during transmission and being terminated at the relaying equipment.
In the present invention according to the claim
4
, the information bits and the check bits may be further divided into M subblocks, where M is a natural number≧2, to compose the Hamming code block having a single subblock of the information bits and the check bits.
Namely, the Hamming code blocks composed of the information bits a
Ishiwatari Junichi
Kuwabara Takashi
Shioda Masahiro
Taniguchi Atsuki
Yamazaki Yukio
Katten Muchin Zavis & Rosenman
Torres Joseph D.
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