Error correcting memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Patent

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Details

365222, 714773, G11C 11403, G11C 2900

Patent

active

060651466

ABSTRACT:
An error-correcting dynamic memory (100) which performs error correction (110) only during refresh or during the second (or subsequent) read of a burst read or during a writeback. Further, the memory may contain an error-correction-code-obsolete bit in addition to data bits and check bits in order to generate check bits during refresh and not during write. This provides error correction without read access delay or write delay at the cost of slightly more exposure to soft errors.

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patent: 4748627 (1988-05-01), Ohsawa
patent: 4758992 (1988-07-01), Taguchi
patent: 4766573 (1988-08-01), Takemae
patent: 5012472 (1991-04-01), Arimoto et al.
patent: 5127014 (1992-06-01), Raynham

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