Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-01-30
2004-08-03
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S769000, C714S785000, C714S804000
Reexamination Certificate
active
06772385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data transfer systems. In particular, the invention relates to an error-correcting method, an error-checking device, a decoding method and a decoder applied to a system for error correction and check of a multidimensional code such as a product code.
2. Description of the Background Art
Image information and the like containing a large amount of information are now recorded, reproduced and transmitted by digital signals in most instances. Accordingly, there arises an increased importance of error correction and error check in order to enhance the reliability of recorded information or transmitted information. Especially real-time recording and reproduction requires high-speed processing for correcting and checking any error in such a large amount of information.
A conventional data transfer system, for example, a recordable and reproducible magneto-optical disk device adds an error-correcting code formed of a product code to received data and stores the data on a recording medium.
The stored data is thereafter called by an error-correcting device as required and any error is corrected. Error check is then carried out by an error detecting code (hereinafter referred to as EDC) to confirm absence of errors, and the data is output to the outside.
In a reproduction-only optical disk device, stored data is similarly called as required by an error-correcting device where any error is corrected. Error check is thereafter performed by an error detecting code to confirm absence of errors. The data is then output to the outside.
Problems of Error Correction and Error Check
According to a conventional error-correcting method, data read from a DVD (Digital Versatile Disk) for example is temporarily stored in a buffer of an external semiconductor memory device such as a Synchronous Dynamic Random Access Memory (SDRAM). The data is then called by an error-correcting device to correct any error.
The DVD employs for example a product code constituted of data arranged in a rectangular shape to which error-correcting codes are added in two directions, i.e., the vertical direction (PO direction) and the horizontal direction (PI direction).
FIG. 32
shows a format of a conventional error-correcting product code for the DVD.
Here, one block refers to data formed of information data arranged in two-dimension in 172 bytes×192 rows to which horizontal 10-byte parity PI (error-correcting inter code) and vertical 16-byte parity PO (error-correcting outer code) are added. The horizontal and vertical directions are also called PI and PO directions respectively in FIG.
32
.
FIG. 33
shows a relation between the error-correcting product code (error-correcting inter code and error-correcting outer code) in FIG.
32
and error detecting codes (EDC).
One block mentioned above is divided into sixteen sectors each consisting of data arrangement in 172 bytes×12 rows. One sector includes a 4-byte EDC at its end.
FIG. 34
shows data arrangement in one sector containing the error detecting code. The bits are numbered in descending order from the leading bit.
The one-sector data are arranged as data from bit data b
16511
to bit data b
0
and bit data b
31
to b
0
correspond to the EDC.
FIG. 35
is a schematic block diagram illustrating a first conventional structure for error correction and error check applied to the DVD data structured as discussed above.
Referring to
FIG. 35
, a basic decoding pattern follows the procedure for example described below.
1. An input signal is stored in a data buffer (SDRAM: Synchronous Dynamic Random Access Memory)
3024
via a data bus
3021
, and a PI direction error-correcting circuit
3020
reads data in PI direction from data buffer
3024
to calculate a syndrome.
2. PI direction error-correcting circuit
3020
detects an error amount and an error position from the value of the PI direction syndrome to correct any error in the data stored in data buffer
3024
.
3. A PO direction error-correcting circuit
3022
reads data in PO direction from data buffer
3024
to calculate a syndrome.
4. PO direction error-correcting circuit
3022
calculates an error amount and an error position from the value of the PO direction syndrome to correct any error in the data stored in data buffer
3024
.
These processes are repeated to correct errors.
5. After the error correction is completed, an error-checking circuit
3023
reads the data from data buffer
3024
to confirm absence of errors by using error detecting codes.
A problem here in these processes is that the error correction and check takes a long time since, after error correction, data buffer (SDRAM)
3024
is accessed again for error check.
For example, in the structure shown in
FIG. 35
, only after error correction of data read from data buffer
3024
is completed, error-checking circuit
3023
reads the data from data buffer
3024
. Relatively time-consuming data reading and writing from and to data buffer
3024
is carried out frequently, resulting in a longer time taken by the processes.
Japanese Patent Laying-Open No. 11-55129 for example discloses a method to overcome this problem.
FIG. 36
is a schematic block diagram illustrating a second conventional structure for error correction and error check disclosed in Japanese Patent Laying-Open No. 11-55129.
The error-correcting and checking device shown in
FIG. 36
is structured to use a data bus shared by an error-correcting circuit and an error-checking circuit.
FIGS. 37
,
38
,
39
and
40
respectively show first to fourth models illustrating a general process followed by the error-correcting and checking device shown in FIG.
36
.
In
FIGS. 37 and 38
, data to be error-checked are shown in a decreased number, i.e., 40 data (10 columns×4 rows) for the purpose of simplifying illustration.
Error check by means of the error-correcting and checking device shown in
FIG. 36
is carried out in two stages.
In the first stage, data is read from a buffer
3034
for error correction in PI direction for example, and the data is transferred in the data arrangement order as shown in
FIG. 37
to a DATA syndrome generating circuit
3036
to calculate a DATA syndrome.
The calculated DATA syndrome is stored in a memory device
3032
.
In the first stage, in addition to the DATA syndrome calculation, an ERROR syndrome is calculated by using an error amount detected by a PI direction error-correcting circuit
3030
according to the data arrangement order shown in FIG.
37
.
In the second stage, an error amount detected by a PO direction error-correcting circuit
3032
is further used to perform subsequent ERROR syndrome calculation according to the data arrangement order shown in FIG.
38
.
Referring to
FIG. 39
, an exclusive-OR operation unit
3035
calculates the exclusive-OR of the two syndromes, DATA syndrome and ERROR syndrome, so as to determine a final check syndrome. Based on the check syndrome, a decision circuit
3031
judges results of error check.
The second-time data reading from data buffer
3034
for generating a check syndrome is thus unnecessary so that fast and parallel error correction and check processes are possible.
Further, in the calculation of the error-correction syndrome by PO direction error-correcting circuit
3032
, if codewords in column
3
(COL
3
) have no error, subsequent detection of an error amount and an error position is skipped. According to this, in the ERROR syndrome calculation, the speed of operation is enhanced by using offset values for the codewords without error as shown in FIG.
40
.
However, this offset calculation requires, in ERROR syndrome generating circuit
3038
, an operating circuit having at least three paths for syndrome calculation corresponding respectively to an operation proceeding through rows one by one in the vertical direction, an operation through columns from one column to the next column, and an operation through columns at every other columns. A problem then arises of increase in the circuit scale.
Problems of Synd
Arisaka Toru
Nagai Hiroki
Ohyama Tatsushi
Yamauchi Hideki
Dildine R. Stephen
Sanyo Electric Co,. Ltd.
Westerman Hattori Daniels & Adrian LLP
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