Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-12-16
2002-08-06
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S763000
Reexamination Certificate
active
06430723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an error correcting device performing error correction for data composed as an error correction data and a data reproducing device reading out data recorded in a recording medium such as a compact disc (CD) or a digital versatile disc (DVD).
2. Description of the Prior Art
First Prior Art
FIG. 39
illustrates a conventional error correcting device for use in a disc reproducing device for reproducing data recorded in a recording medium such as a DVD. The reproducing device comprises a receiving circuit
1
receiving data read from a disc by an optical pickup and composed as an error correcting code. Neither disc nor pickup is shown. The receiving circuit
1
then decodes the received data and then writes the decoded data through an arbitrator
2
into a storage device
3
such as a RAM. The data received by the receiving circuit
1
sometimes contains an error when the surface of the disc is damaged or dirty due to adherence of dirt such as fingerprints. In such a case, an error correcting circuit
4
reads out the data the receiving circuit
1
has written into the storage device
3
to thereby detect an error in the data. When detecting a correctable error, the error correcting circuit
4
corrects the data containing the error, writing the corrected data through the arbitrator
2
into the storage device
3
.
The conventional error correcting device further comprises a transmission circuit
5
reading out the data having been corrected by the error correcting circuit
4
through the arbitrator
2
from the storage device
3
. The transmission circuit
5
then transmits the read data to a reproduction system (not shown) for reproduction of the data as image or sound. The arbitrator
2
serves as a memory interface for arbitrating access of the receiving circuit
1
, the error correcting circuit
4
and the transmission circuit
5
to the storage device
3
.
FIG. 40
shows a concept of storage area of the storage device
3
. The storage area of the storage device
3
is divided into three areas A, B and C. Each area has a storage capacity set to be equal to that of one block which is a unit for which the error correction is performed with use of the error correcting code. For example, as shown in
FIG. 41
, when the data received by the receiving circuit
1
is to be written into the area A in a phase, the data the receiving circuit
1
has written into the area C in the last phase is an object for error detection and correction, whereas the data which is stored in the area B and the error of which has been corrected by the error correcting circuit
4
in the last phase is an object to be transmitted by the transmission circuit
5
.
In a next phase, the received data is to be stored in the area B, the error detection and correction are to be performed for the data stored in the area A, and the data stored in the area C is to be transmitted. Thus, the three areas are sequentially switched among three processes of data reception, error detection and correction, and data transmission. In this case, the receiving circuit
1
delivers both to the error correcting circuit
4
and to the transmission circuit
5
a status signal indicative of completion of reception of one block of data. Each of these circuits
4
and
5
confirms receipt of the status signal before performing the process for a new area.
According to the above-described system, the processes of data reception, error correction and data transmission can concurrently be executed in a time sharing. Accordingly, an operating speed of each circuit need not be increased to a large value. However, the storage device
3
requires a storage capacity at least three times larger than the one corresponding to one block of data. This results in a problem that a circuit is rendered large-sized.
In order to solve the above-mentioned problem, the inventors proposed an arrangement shown in FIG.
42
. Specifically, a storage device with a storage capacity twice as large as the data block capacity (only areas A and B) is used instead of the storage device
3
. While the receiving circuit
1
is writing data into either one of the areas A and B, the error correcting circuit
4
perform an error correction for the data stored in the other area and thereafter, the transmission circuit
5
transmits the error-corrected data. The two areas are thus switched therebetween.
According to the proposed system described above, the storage capacity of the storage device can be reduced. However, the error correction for one block of data by the error correcting circuit
4
and the transmission of the corrected data by the transmission circuit
5
need to be serially executed and completed within a time of write of another block of data into one of the areas by the receiving circuit
1
. In this arrangement, accordingly, operating speeds of the error correcting circuit
4
and the transmission circuit
5
need to be increased. This results in a problem that the conditions of design of circuits including the circuits
4
and
5
is rendered more rigorous.
Second Prior Art
The inventors proposed an arrangement as shown in
FIG. 43
as an error correcting device for use in a disc reproducing device for reproducing data stored in the CD or the DVD. In this arrangement, the receiving circuit
6
receives data read from a disc by an optical pickup and composed as an error correcting code, decoding the received data. Neither disc nor pickup is shown. The receiving circuit
1
then writes the decoded data through an arbitrator
7
into a storage device
8
such as a RAM.
An error correcting circuit
9
reads out the data the receiving circuit
6
has written into the storage device
8
to thereby detect an error in the data. When detecting a correctable error, the error correcting circuit
9
corrects the data containing the error, writing the corrected data through the arbitrator
7
into the storage device
8
.
A transmission circuit
10
reads out the corrected data through the arbitrator
7
from the storage device
8
. The transmission circuit
10
then transmits the read data to a reproduction system (not shown) for reproduction of the data as image or sound. The arbitrator
7
serves as a memory interface for arbitrating access of the receiving circuit
6
, the error correcting circuit
9
and the transmission circuit
10
to the storage device
8
. A syndrome calculating circuit
11
obtains data directly from the receiving circuit
6
to calculate syndrome from the error correcting code, delivering the result of calculation to the error correcting circuit
9
.
For example, a DVD employs, as the error correcting code, a Reed-Solomon product code constituted by two sequences of error correcting codes comprising an inner parity (PI) code and an outer parity (PO) code. Accordingly, the receiving circuit
6
writes data of one block of product code into the storage device
8
and thereafter, the error correcting circuit
9
reads out the stored data from the storage device
8
to perform the error correction. Now assume an arrangement as shown in FIG.
43
. In this arrangement, the syndrome calculating circuit
11
calculates syndrome concerning, for example, rows of PI code, so that the error correcting circuit
9
can start detection of error concerning a first row of PI code before the receiving circuit
6
finishes writing one block of product codes into the storage device
8
. Consequently, a time required for the error detection and correction can be reduced.
However, in the above-described system, when disturbance occurring in a receiving system at the receiving circuit
6
side interrupts data reception, the syndrome calculating circuit
11
cannot obtain the number of units of information symbols required for the calculation of syndrome, resulting in a problem that the calculation of syndrome cannot properly be performed.
Further, the storage device
8
retains data written thereinto in the past and being currently meaningless due to interruption of data reception. I
Hikimura Akira
Kodama Kunihiko
Moriyama Katsutoshi
Kabushiki Kaisha Toshiba
Tu Christine T.
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