Error correcting/decoding apparatus and error correcting/decodin

Details Error correcting/decoding apparatus and error correcting/decodin Error correcting/decoding apparatus and error correcting/decodin

1997-10-17

2000-05-09

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714794, 714795, G06F 1110

Patent

active

06061823&

ABSTRACT:
The demodulator demodulates received data, the Viterbi decoder decodes the received data to a bit sequence with the Viterbi algorithm according to the soft-decision estimate generated in demodulation and at the same time appends a reliability to each bit in the bit sequence. Then, a CRC circuit determines whether any error is detected or not by executing CRC on the decoded bit sequences, and, if no error is detected, the bit sequence is output as decoded data. On the other hand, if any error is detected, bit inversion is executed in the ascending order of sums of reliability for bits to be inverted until no error is detected by the CRC circuit. For this reason, the case of error detection is decreased and the work load for computing is decreased.

REFERENCES:
patent: 5321705 (1994-06-01), Gould et al.
patent: 5361266 (1994-11-01), Kodama et al.
patent: 5577053 (1996-11-01), Dent
patent: 5770927 (1998-06-01), Abe

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