Error correcting code scheme

Details Error correcting code scheme Error correcting code scheme

2005-01-25

2005-01-25

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S766000

Reexamination Certificate

active

06848070

ABSTRACT:
An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.

REFERENCES:
patent: 5740188 (1998-04-01), Olarig
patent: 5867511 (1999-02-01), Arimilli et al.
patent: 6038693 (2000-03-01), Zhang
patent: 6216247 (2001-04-01), Creta et al.

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