Error control apparatus and method using cyclic code

Details Error control apparatus and method using cyclic code Error control apparatus and method using cyclic code

2001-07-06

2003-02-04

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S701000, C714S746000, C714S781000

Reexamination Certificate

active

06516439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an error control apparatus and method using a cyclic code in communication, and more particularly, to an error control apparatus and method using a communication system that may switch between communication using data interleaving and communication not using data interleaving.
2. Description of the Background Art
In recent years, communication devices using radio communication such as a portable telephone is being widespread. The radio communication does not require a telephone line or the like in an ordinary telephone system and can be performed by providing base stations in proper places. Consequently, the radio communication is most suitable to use in an area where cost of laying a telephone line seems to be excessive. Moreover, since locations where communication can be conducted are not always limited, the radio communication is expected to be more widely used in the future.
In the radio communication, digital communication is mainly used. Particularly, in the radio communication, for example, in order to protect privacy of conversation by telephone, it is preferable to use the digital communication.
In the digital communication, there is a case such that an error control system in which a coding system using an error correcting code and a CRC code are combined is used. Particularly, as seen in a part of the standards of recent portable telephone systems, at the time of transmission from a base station to a mobile station, when the state of communication is seen from the mobile station and the quality of a radio line is good, a CRC code obtained by CRC which does not perform interleaving is added to data and the resultant is transmitted. When the quality of the radio line is not good, data is coded by an error correcting code, and a CRC code obtained by the CRC performing interleaving is added to data. In such a manner, there is a case that the system of the CRC code changes according to the line quality.
Data that is not interleaved includes, like reception data
120
shown in
FIG. 9
, 224 bits of data D
0
to D
223
(208 bits of data from D
0
to D
207
and 16 bits of CRC bits from D
208
to D
223
). The data bits are sequentially transmitted in accordance with the order. The data is stored into a reception buffer in this order, sequentially read in this order, and decoded for an error control by the CRC. As an example, the code length of 224 bits, 16-bit CRC, and 16-stage interleaving are assumed here.
Referring to
FIG. 10
, reception data
130
is interleaved not in the order of D
0
to D
223
but in the order of D
0
, D
16
, D
32
, . . . , D
209
, D
1
, D
17
, D
33
, . . . , D
210
, . . . , D
222
, D
15
, D
31
, D
47
, . . . , D
207
, D
223
. The interleaved reception data
130
is transmitted, read in this order as shown by arrows
132
, and decoded for an error control by the CRC. Particularly, such interleaving is performed by adding an error correction signal when line quality is poor.
Data formatting with/without interleaving is done on the base station side. A mobile unit cannot know whether data received from the base station is interleaved data or not. Conventionally, the mobile unit performs error detection by a CRC circuit on the assumption that the received data is interleaved. When there is no error, it is determined that the received data is in an interleaved format and the process is continued. When there is an error, it is determined that the received data is in a format without interleaving. The mobile unit regards the data as data that is not interleaved and performs error detection again by the CRC circuit. When a CRC error is further detected in the process, a proper error process such as retransmission of data is performed. When the error correcting code is added, error correction by the error correcting code is also conducted at this time. A technique of transmitting data by adding the error correcting code is called an FEC (Forward Error Correction), and a circuit for the FEC is called an FEC circuit. Since the invention relates to a CRC decoding process and does not relate to the FEC, in order to make the description regarding the invention clear, the FEC will not be considered in the following description.
An example of a circuit for realizing the above-described CRC process is shown in FIG.
7
. Referring to
FIG. 7
, a conventional error control decoding unit
90
includes: a reception data buffer
50
for storing data received from a base station; a deinterleaver
52
for deinterleaving data by reading data in accordance with a predetermined order on the assumption that data stored in the reception data buffer
50
is interleaved data (in an interleave format); an FEC
54
for receiving an output of the deinterleaver
52
; an FEC
56
for receiving data read directly from the reception data buffer
50
; a selector
100
for selecting and outputting either data of the FEC
56
or data of the FEC
54
; and a CRC circuit
58
for receiving an output of the selector
100
and calculating CRC of the data.
Referring to
FIG. 11
, as is well known, the CRC circuit
58
includes: a plurality of 1-bit registers CR
0
to CR
15
that are connected in series so as to sequentially shift data (the number of the 1-bit registers is determined by a CRC generation polynomial); adders
142
and
144
each inserted in front of the 1-bit register in a position corresponding to a coefficient except for 0 in coefficients in each term in the CRC generation polynomial, for performing addition by using 2 as a modulus between data supplied via a data line
140
and an output of the immediately preceding 1-bit register and supplying the result to the immediately following 1-bit register; and an adder
146
for performing addition using 2 as a modulus between input data and an output of the last 1-bit register CR
15
and supplying the result to the head 1-bit register CR
0
and the adders
142
and
144
via the data line
140
.
FIG. 11
shows the CRC circuit corresponding to the following generation polynomial.
g
(
x
)=
x
16
+x
22
+x
5
+1
The CRC circuit is substantially a dividing circuit.
In the CRC circuit, a predetermined initial value is set in each of the 1-bit registers in the beginning, reception data is supplied as input data bit by bit, and the value is sequentially shifted by the 1-bit registers. When all of bits are inputted, the values held in the 1-bit registers CR
0
to CR
15
are a reminder of division, that is, CRC bits. Usually, when the CRC bit is 0, it is determined that there is no error. When the CRC bit is not 0, it is determined that an error occurs.
The error detection using the circuit is performed by processes shown in the flowchart of FIG.
12
. Specifically, a mobile unit is started to receive a unit (step S
2
). Assuming first that the reception data are interleaved, data deinterleaved via the deinterleaver
52
shown in
FIG. 7
is selected by the selector
100
and is subjected to the CRC process in the CRC circuit
58
(step S
30
). As a result, if there is no CRC error, the control advances to step
8
and if there is a CRC error, the control advances to step S
34
(determination in step S
32
).
When there is no CRC error, it means that data transmitted from the base station is interleaved. Consequently, a receiving process is performed on the condition that the data is interleaved. Specifically, first, in step S
8
, whether the unit received in step S
2
is the head unit or not is determined. When it is not the head unit, the unit is discarded in step S
14
, and the control returns to step S
2
.
When it is determined in step S
8
that the unit received in step S
2
is a head unit, in step S
10
, it is determined that the data is interleaved one, a following unit is received, and the CRC process is performed on the following unit. That is, in the subsequent processes, the selector
100
selects an output of the FEC
54
. Subsequently, in step S
12
, whether there is a following unit or not is determined. If YES, the control

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