Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-09-27
1998-12-01
Pan, Daniel H.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711153, 711152, G06F 1214, G06F 1316
Patent
active
058450718
ABSTRACT:
The multi-node multiprocessor system with globally shared memory is partitioned into groups of nodes called error containment clusters of nodes or ECCNs. The nodes would be partitioned such that an ECCN resides on a column of nodes or a row of nodes. Within each ECCN there is coherent memory sharing. Between the ECCNs, the communication is through a messaging protocol. The memory within each node is also partitioned into protected and unprotected memory. Unprotected memory is used for messaging and protected memory is used for sharing. A failure in an error containment cluster would corrupt the memory within that cluster, specifically the protected memory within that cluster and also the unprotected memory used by that cluster to communicate with the other clusters. However, the other clusters could continue to run because their protected memory would be unaffected, and could continue to communicate through the remaining unprotected memory.
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IEEE Standard for Scalable Coherent Interface (SCI), IEEE Std. 1596-1992 ISBN 1-55937-222-2; pp. 1-40, 199-235.
John Chapin, Mendel Rosenblum, Scott Devine, Tirthankar Lahiri, Dan Teodosiu, and Anoop Gupta; "Hive: Fault Containment for Shared-Memory Multiprocessors"; this work first appeared in the 15th ACM Symposium on Operating Systems Principles, Dec., 1995.
Chastain David M.
Gant Alan D.
Patrick David M.
Hewlett-Packard Co.
Pan Daniel H.
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