Error burst detector for lowering receiver bit error rate

Details Error burst detector for lowering receiver bit error rate Error burst detector for lowering receiver bit error rate

1996-12-23

1999-08-24

Palys, Joseph E.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

371 381, G06F 1100

Patent

active

059420030

ABSTRACT:
A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator modified to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

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Sklar, Bernard, Digital Communications: Fundamentals & Applications, Prentice Hall, Englewood Cliffs, NJ, pp. 263-365, 1988.

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