Error absorbing system in a neuron computer

Details Error absorbing system in a neuron computer Error absorbing system in a neuron computer

1990-02-28

1993-06-01

Fleming, Michael R.

G06F 1518

Patent

active

052167461

ABSTRACT:
An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

REFERENCES:
patent: 4807168 (1989-02-01), Moopenn et al.
patent: 4885545 (1989-12-01), Sanielevici
patent: 4906865 (1990-03-01), Holler
patent: 4914319 (1990-04-01), Hashimoto
patent: 4950923 (1990-08-01), Garuts
patent: 4962342 (1990-10-01), Mead et al.
patent: 4973975 (1990-11-01), Yamazaki et al.
patent: 4974169 (1990-11-01), Engel
patent: 4987323 (1991-01-01), Fujita
patent: 4988891 (1991-01-01), Mashiko
patent: 5131072 (1992-07-01), Yoshizawa et al.
Furman et al., "An Analog CMOS Backward Error-Propagation LSI", First Annual INNS Symposium, Sep. 1988.
Bailey et al., "Why VLSI Implementations of Associative VLCNs Require Connection Multiplexing", IEEE 2nd Intl. Conf. on Neural Networks, 1988, pp. II-173-II-180.
Mead et al., Analog VLSI Implementation of Neural Systems, Kluwer Academic Publ., 1989, pp. 135-169.
Eberhardt et al., "Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI `Building Block` Chips", IJCNN, Jun. 1989, vol. 2, pp. II-183-II-190.

Affiliated with

Also associated with

Rating

Error absorbing system in a neuron computer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error absorbing system in a neuron computer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error absorbing system in a neuron computer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1821410