Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-18
2009-10-27
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07610544
ABSTRACT:
A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.
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Chase Shelly A
Shemwell Charles
Telegent Systems, Inc.
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