Erasure-and-single-error correction decoder for linear block...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S746000, C714S799000

Reexamination Certificate

active

06986092

ABSTRACT:
Techniques for efficiently performing erasure-and-single-error correction block decoding on a received block of symbols previously coded column-wise with an (N, K) linear block code and row-wise with an error detection code (e.g., a CRC code). Initially, each row of the received block is marked as either an erased row or an un-erased row. To perform erasure-and-single-error correction block decoding on the received block, a codeword corresponding to a column of the received block containing an undetected symbol error is initially identified. The location of the symbol error in the codeword is then determined based on a particular block decoding scheme and corresponding to the selected (N, K) block code. The row of the received block containing the symbol error is then marked as an erased row. Block decoding may then be performed for the received block with the newly marked erased row containing the symbol error.

REFERENCES:
patent: 5446759 (1995-08-01), Campana, Jr.
patent: 5636253 (1997-06-01), Spruyt
patent: 2002/0075830 (2002-06-01), Hartman
patent: 2002/0106190 (2002-08-01), Nygren et al.
patent: 0407101 (1991-01-01), None
Rizzo, Luigi.,On the feasibility of software FEC; Dip. di Ingegneria dell'Informazione, Universita di Pisa, via Diotisalvi 2—56126 Pisa (Italy).
Katayama, Y et al: “One-Shot Reed-Solomon Decoding For High-Performance Dependable Systems”, 2000 IEEE International Networks, NY, USA, Jun. 25, 2000, pp. 390-399.
Alzahrani, F et al: “On-Chip TEC-QED ECC For Ultra-Large, Single-Chip Memory Systems”, Proceedings IEEE International Conference On Computer Design, Oct. 10, 1994, pp. 132-137.
Franklin, M et al: “Theory and Techniques For Testing Check Bits Of Rams With On-Chip ECC”, IEICE Transactions On Information and Systems, Tokyo, Japan, vol. E76-D, No. 10, Oct. 1, 1993, pp. 1243-1252.
Nagvajara, P: Multichip Module Diagnosis, Electro/94 International Conference Proceedings, Boston, MA, IEEE, USA. Combined Volumes, May 10, 1994, pp. 793-802.

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