Erasing method in nonvolatile semiconductor memory device

Details Erasing method in nonvolatile semiconductor memory device Erasing method in nonvolatile semiconductor memory device

1998-03-18

1999-08-03

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 365218, G11C 1604

Patent

active

059333677

ABSTRACT:
A control gate is loaded with a negative voltage pulse and a source region is loaded with a positive constant voltage pulse while a drain region is at a floating state. More specifically, the absolute value of the voltage applied to the control gate is increased with time for a period from the start of a memory erasing action (the application of the pulse voltage) to 2 msec and then remains constant from 2 msec to the end of the memory erasing action. As the result, a potential difference between the source region and the control gate at the start of the memory erasing action is smaller than that at the end of the memory erasing action. This prevents the tunnel oxide layer from receiving a high electric field stress at the start of the memory erasing action, thus improving the write/erase endurance.

REFERENCES:
patent: 5452248 (1995-09-01), Naruke et al.
patent: 5726933 (1998-03-01), Lee et al.
patent: 5781477 (1998-07-01), Rinerson et al.

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