Erasing method for a non-volatile memory

Details Erasing method for a non-volatile memory Erasing method for a non-volatile memory

1996-12-24

1998-10-06

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 700

Patent

active

058187634

ABSTRACT:
The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps of: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

REFERENCES:
patent: 5270979 (1993-12-01), Harari et al.
patent: 5434825 (1995-07-01), Harari
patent: 5557572 (1996-09-01), Sawada et al.
patent: 5596530 (1997-01-01), Lin et al.
patent: 5615148 (1997-03-01), Yamamura et al.

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