Erase voltage control circuit for an electrically erasable non-v

Details Erase voltage control circuit for an electrically erasable non-v Erase voltage control circuit for an electrically erasable non-v

1997-01-23

1998-02-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Erase

36518529, 365226, G11C 700

Patent

active

057217076

ABSTRACT:
An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the control electrode of the memory cell and means for electrically coupling the first electrode to a voltage supply. The circuit further includes control means for selectively deactivating the negative voltage generator means when a current supplied by the voltage supply to the first electrode of the memory cell reaches a predetermined value.

REFERENCES:
patent: 5231602 (1993-07-01), Radjy et al.
patent: 5365121 (1994-11-01), Morton et al.

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