Erase verifying circuit for a nonvolatile semiconductor memory w

Details Erase verifying circuit for a nonvolatile semiconductor memory w Erase verifying circuit for a nonvolatile semiconductor memory w

1996-02-05

1997-09-23

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518509, 36518512, 36518517, 36518523, 36518533, 36518905, 36523006, G11C 1606

Patent

active

056711786

ABSTRACT:
An EEPROM with improved reliability irrespective of the occurrence of an open normal bit line includes an array of rows and columns of floating gate type normal and redundant memory cells, a plurality of normal bit lines each connected to the normal memory cells in a corresponding column of the array, a plurality of redundant bit lines each connected to the redundant memory cells in a corresponding column of the array, and a page buffer connected to the normal and redundant bit lines for sensing and storing pass and fail data read-out from selected normal cells in a desired row during an erase verifying operation of the memory after erasure of the selected normal memory cells. The page buffer stores pass data representing successful erasure of the selected normal memory cells and fail data associates with at least one defective normal bit line. A data changing circuit is connected to the page buffer to change the fail data associated with the defective bit line stored in the page buffer into pass data.

REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 5515324 (1996-05-01), Tanaka

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