Erase and program verification circuit for non-volatile memory

Details Erase and program verification circuit for non-volatile memory Erase and program verification circuit for non-volatile memory

1993-08-31

1995-10-31

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

36518909, 36518522, G11C 2900, G11C 1600

Patent

active

054635861

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to the design of erasable and programmable non-volatile memory devices; and more particularly to circuits for verifying a programmed or erased state of memory cells in the device, suited for flash EPROM or EEPROM memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as the erasable-programmable read only memory (EPROM). Two popular EPROM designs are distinguished in the manner in which erasure of the memory cells is carried out. The first is referred to as the EEPROM which uses an electrical erasure routine that involves relatively high voltage. A second member of this class is known as the flash EPROM which uses a lower voltage erasing technique.
Both the flash EPROM and EEPROM technologies are based on a memory cell which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons, which causes the turn on threshold of the memory cell to increase. Thus, when programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
Both the flash EPROM and EEPROM memory cells suffer the problem of over-erasure. Over-erasure occurs if, during the erasing step, too many electrons are removed from the floating gate leaving a slight positive charge. This biases the memory cell slightly on, so that a small current may leak through the memory cell even when it is not addressed. A number of over-erased cells along a given bit line can cause an accumulation of leakage current sufficient to cause a false reading. The regular EEPROM design uses a two transistor cell structure which includes a pass gate that isolates the memory cell from the bit line, so that unselected memory cells do not contribute leakage current to the bit line. The flash EPROM cell does not use the isolation transistor, so over-erasure causes a significant problem in the flash EPROM design.
Over-erasure also illustrates an important phenomenon involved with the programming and erasing of floating gate memory cells. That is, the amount of charge which is moved into the floating gate during a given programming phase or moved out of the floating gate during a given erasure phase cannot always be tightly controlled. This amount of charge depends on such factors as the temperature of the cell at the time of the operation, variations in the cells which occur due to processing technology, ceil aging, and other factors.
Therefore, commercial flash EPROM designs include circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,188, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth. The prior art devices include a first mode for verifying the programming of the cell during which the potential supplied to the control gate of the cell (across word lines in the memory array) is increased above the normal read potential. Thus, the Jungroth patent provides for applying a 5 V potential to the cell for normal read operations, and a higher potential of approximately 7.5 V during the program verify. By performing program verify with a higher voltage on the control gate, the circuit ensures that the programming step resulted in injection of a sufficient number of electrons into the floating gate to raise the turn on threshold with a safe margin over the minimum amount required. Similarly, during erase verify, the voltage on the control gate is reduced by Jungroth to approximately 3.25 V instead of 5 V. If the cell conducts

REFERENCES:
patent: 4875188 (1989-10-01), Jungroth
patent: 5091888 (1992-02-01), Akaogi
patent: 5117394 (1992-05-01), Amin et al.
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5163021 (1992-11-01), Mehrotra et al.

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