Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-12-19
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S402000, C257S515000
Reexamination Certificate
active
06222224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory. In particular, the present invention relates to an EEPROM (electrically erasable and programmable read-only memory) capable of suppressing threshold-voltage variations among memory cells and preventing soft-writing (erroneous writing) in memory cells, semiconductor integrated circuit device having the EEPROM and a method of manufacturing such an EEPROM.
2. Description of the Prior Art
Semiconductor memories are roughly classified into RAMs (random-access memories) and ROMs (read-only memories). The RAMs allow to rewrite information stored therein at any time. The ROMs allow to write information into them during manufacturing or after manufacturing, and the information once written therein is completely unable to rewrite or is difficult to rewrite. Generally, the RAMs are volatile memories that hold information only with the supply of electric power, and the ROMs are nonvolatile memories that hold information even without power supply.
The ROMs include masked ROMs, EPROMs (erasable and programmable read-only memories), EEPROMs, etc. The EEPROMs are one of the promising semiconductor memories because they are electrically erasable and programmable by the user. Among the EEPROMs, NAND-type EEPROMs have a possibility of replacing magnetic disks because they may have very small memory cells to realize high integration and large capacity.
However, the NAND-type EEPROMs have some problems.
Memory cells of the EEPROM are made of insulated-gate FETs (field effect transistors), and the threshold voltages of these FETs vary from one to another due to variations in the thicknesses of gate insulation films and variations in the concentrations of impurities in channel regions. These variations are produced during the manufacturing of the EEPROM. The threshold-voltage variations reduce a margin in determining whether information read out of a given cell is “0” or “1” and may cause a read error.
The EEPROMs frequently employ a trench structure as an element isolating region between memory cells, to realize high integration and large capacity. The trench structure is composed of a trench formed from the surface of a substrate in the depth direction and insulating material filled in the trench. In a read operation of an insulated-gate FET serving as a memory cell, a read voltage is applied to a control gate electrode of the FET. The read voltage may cause an electric field concentration at a corner of the trench that defines the width of a channel region. During the read operation, the electric field concentration gradually accumulates a charge by injecting electrons from the channel region into a floating gate electrode through a tunnel insulation film, thereby causing soft-writing (erroneous writing).
SUMMARY OF THE INVENTION
To solve these problems, an object of the present invention is to provide a nonvolatile semiconductor memory capable of reducing variations in the threshold voltages of insulated-gate FETs that form memory cells of the memory, causing no error in reading information out of the memory, and being highly reliable.
Another object of the present invention is to provide a nonvolatile semiconductor memory capable of causing no soft-writing nor a read error in reading information out of the memory and being highly reliable.
Still another object of the present invention is to provide a method of manufacturing such a nonvolatile semiconductor memory.
Further, object of the present invention is to provide a semiconductor integrated circuit device to have a nonvolatile semiconductor memory.
In order to accomplish the objects, the present invention provides a nonvolatile semiconductor memory having memory cells each having an insulated-gate FET that stores information in an information storage part according to a charge injected from a channel region into the information storage part through a tunnel insulation film. The memory is characterized by a semiconductor region formed at the surface of the channel region of the insulated-gate FET. The semiconductor region has the same conductivity type as a channel conductivity type and functions to reduce the strength of an electric field at the surface of the channel region.
The concentration of impurities in the semiconductor region has a peak at the surface of the channel region. The semiconductor region makes zero of the effective strength of an electric field at the surface of the channel region in an information read operation of the memory cell. A space charge in the semiconductor region is set to be equal to that in a well region or a semiconductor substrate where the insulated-gate FET is formed. The space charge in the well region or semiconductor substrate is determined by an electron charge quantity, the concentration of impurities in the well region or semiconductor substrate, and the maximum width of a depletion layer in the well region or semiconductor substrate. The space charge in the semiconductor region is determined by an electron charge quantity, the concentration of impurities in the semiconductor region, and the maximum width of a depletion layer in the semiconductor region. The diffusion depth of the semiconductor region is set to be equal to the maximum width of the depletion layer that determines the space charge in the semiconductor region.
The insulated-gate FET includes floating gate electrode and a control gate electrode, and the floating gate electrode serves as the information storage part. It is preferable that the insulated-gate FET is of an n-channel type and the semiconductor region is of an n-type. The n-type semiconductor region has a lower impurity concentration than the source and drain regions of the insulated-gate FET.
The memory cells may electrically be connected in series to form a NAND-type EEPROM. The channel region of the insulated-gate FET is formed at the surface of a silicon semiconductor substrate. The information storage part, i.e., the floating gate electrode is made of gate electrode material that has a Fermi level at substantially the center of a band gap of the silicon semiconductor substrate. The gate electrode material may be refractory metal such as W, Ti, Mo, and Co, or silicide that is a compound of refractory metal and silicon. The present invention also provides a multivalued nonvolatile semiconductor memory having memory cells each storing any one of at least two values. Further the present invention also provides a semiconductor integrated circuit device having a nonvolatile semiconductor memory.
The semiconductor region of the nonvolatile semiconductor memory of the present invention reduces the strength of an electric field at the surface of the channel region, to suppress variations in the threshold voltages of the memory cells even if the insulated-gate FETs serving as the memory cells involve variations in the thicknesses of the tunnel insulation films (gate insulation films) and variations in the concentrations of impurities in the channel regions. Even if the concentration of impurities at the surface of the semiconductor substrate of the insulated-gate FETs varies from cell to cell, no variations occur in the threshold voltages of the cells. This results in improving a margin in testing read information, preventing a read error, and improving the reliability of the memory.
The nonvolatile semiconductor memory of the present invention may have an element isolation region made of a trench formed from the surface of the channel region in the depth direction and insulating material filled in the trench. The semiconductor region reduces the strength of the electric field at the surface of the channel region, and at the same time, relaxes electric field concentration in the channel region at a corner of the trench.
The semiconductor region of the nonvolatile semiconductor memory having the trench struc
Eckert II George C.
Foley & Lardner
Kabushiki Kaisha Toshiba
Lee Eddie C.
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