Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-05-03
2001-07-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S158000, C365S171000, C365S173000
Reexamination Certificate
active
06259644
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to data storage devices. More specifically, the present invention relates to a data storage device including a resistive cross point memory cell array and circuitry for sensing resistance states of memory cells in the array.
Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that is being considered for long term data storage. Performing read and write operations in MRAM devices would be orders of magnitude faster than performing read and write operations in conventional long term storage devices such as hard drives. In addition, the MRAM devices would be more compact and would consume less power than hard drives and other conventional long term storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
The memory cell stores a bit of information as an orientation of a magnetization. The magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’
The magnetization orientation affects the resistance of a memory cell such as a spin dependent tunneling junction device. For instance, resistance of a memory cell is a first value R if the magnetization orientation is parallel, and the resistance of the memory cell is increased to a second value R+&Dgr;AR if the magnetization orientation is changed from parallel to anti-parallel. The magnetization orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance state of the selected memory cell.
Sensing the resistance state of a single memory cell in the array can be unreliable. All memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns (the array of memory cells may be characterized as a cross point resistor network).
Moreover, if the memory cell being sensed has a different resistance state due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to parasitic or “sneak path” currents. The parasitic currents can interfere with the sensing of the resistance states.
There is a need to reliably sense the resistance states of memory cells in MRAM devices.
SUMMARY OF THE INVENTION
This need is met by the present invention. According to one aspect of the present invention, a read operation on a selected memory cell in a resistive cross point memory cell array is performed by applying a first potential to a bit line crossing the selected memory cell and a second potential to a word line crossing the selected memory cell; applying a third potential to a subset of unselected word and bit lines; and determining the resistance state of the selected memory cell while the potentials are being applied to the selected lines and subset of unselected lines. The third potential is equal to the first potential.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
REFERENCES:
patent: 5654566 (1997-08-01), Johnson
patent: 5991193 (1999-11-01), Gallagher et al.
patent: 6034887 (2000-03-01), Gupta et al.
patent: 6097626 (2000-08-01), Brug et al.
patent: 6111783 (2000-08-01), Tran et al.
patent: 6128239 (2000-10-01), Perner
patent: 19744095A1 (1997-10-01), None
Brug James A
Perner Frederick A
Tran Lung T
Auduong Gene N.
Hewlett-Packard Co
Nelms David
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