Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-01-27
2010-11-30
Ngo, Chuong D (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S819000
Reexamination Certificate
active
07844651
ABSTRACT:
An equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay may improve group delay characteristics in the equalizer. The equalizer circuit may include a first low pass filter configured to filter a received input signal to output a filtered input signal, and a gain control circuit connected to an output terminal of the first low pass filter, and configured to modulate a gain of a transfer function for the equalizer. The equalizer may include a group delay compensation circuit connected to the output terminal of the first low pass filter and configured to compensate for a group delay of the input signal, and a second low pass filter connected to the output terminal of the first low pass filter.
REFERENCES:
patent: 5235540 (1993-08-01), De Veirman
patent: 6407875 (2002-06-01), Pierson
patent: 6472932 (2002-10-01), Morie et al.
patent: 6522707 (2003-02-01), Brandstetter et al.
patent: 2002-8314 (2002-01-01), None
patent: 1998-0014110 (1998-06-01), None
patent: 1020020003724 (2002-01-01), None
Korean Office Action dated Aug. 30, 2005.
Han Yun-Cheol
Jin Woo-Kang
Harness & Dickey & Pierce P.L.C.
Ngo Chuong D
Samsung Electronics Co,. Ltd.
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