Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-29
2005-11-29
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S135000
Reexamination Certificate
active
06970977
ABSTRACT:
In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.
REFERENCES:
patent: 6493801 (2002-12-01), Steely et al.
patent: 6557084 (2003-04-01), Freerksen et al.
patent: 6587926 (2003-07-01), Arimilli et al.
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Baryla Robert J.
Buzby Wayne R.
McCulley Lowell D.
Ryan Charles P.
Shelly William A.
Bull HN Information Systems Inc.
Doan Duc T
Driscoll Faith F.
Ellis Kevin L.
Phillips James H.
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