EPROM with trench in thick field oxide

Details EPROM with trench in thick field oxide EPROM with trench in thick field oxide

1994-05-12

1996-03-12

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257322, 257397, 257513, H01L 29788

Patent

active

054988918

ABSTRACT:
An erasable-programmable read only memory (EPROM) allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM includes a semiconductor substrate, a field insulating layer defining a device formation region of the semiconductor substrate, a gate insulating layer and a floating gate formed on the field insulating layer and the field insulating layer. The EPROM further includes a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer so that one of the side walls of the trench insulating layer is self-aligned with the end face of the floating gate. A first interlaminar insulating layer covers the floating gate, and a control gate is located above the first interlaminar insulating layer. A second interlaminar insulating layer is formed over the control gate and a bit line is formed on the second interlaminar insulating layer.

REFERENCES:
patent: 4326331 (1982-04-01), Guterman
patent: 4679304 (1987-07-01), Bois
patent: 4713677 (1987-12-01), Tigelaar et al.
patent: 5051795 (1991-09-01), Gill et al.
patent: 5111257 (1992-05-01), Andoh et al.
patent: 5451803 (1995-09-01), Oji et al.

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