EPROM structure for a semiconductor memory

Details EPROM structure for a semiconductor memory EPROM structure for a semiconductor memory

2000-09-30

2004-02-10

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S681000, C257S687000

Reexamination Certificate

active

06690057

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an electronic memory device, and in particular an EPROM (erasable and programmable read-only memory) structure for a nonvolatile semiconductor memory with a plurality of memory cells, each of which has a floating gate transistor, which can be programmed by hot electrons and can be erased by UV light.
EPROM structures are used to build non-voltile semiconductor memories, especially for integrated circuits (embedded EPROM) and generally in computers or in microprocessor-controlled devices for storing programs and/or data that must be retained without a supply voltage.
Each memory cell of an EPROM structure generally has two transistors, namely a selection or access transistor that selects the memory cell, and a floating gate transistor, whose floating gate represents an erased or programmed state according to its positive or negative charge.
To program the memory cells, voltages of at least eight (8) volts are generally needed at the cell level and consequently voltages of about ten (10) volts for the pass gates. In the case of known EPROM structures, these voltages must be applied selectively to each memory cell that is to be programmed or erased. This implies a necessity for transistors that can switch these voltages. Since each memory cell must be selected, these transistors furthermore must be sufficiently small so that the entire structure and thus the memory will not become disproportionately large.
One problem is that conventionally produced integrated circuits as well as their production methods are designed for five (5) volts or less. For a conventional production process for integrated circuits to handle the high voltages necessary to embed EPROM structures, numerous additional process steps (generally about five to eight masking steps) are generally necessary. This makes the entire process and thus the integrated circuit substantially more expensive.
U.S. Pat. No. 5,212,541 discloses an EPROM structure, each of whose memory cells includes a floating gate transistor, which can be written (programmed) by hot electrons and erased by UV light. These memory cells can be rather easily manufactured with a known CMOS production processes. However, their disadvantage is that a voltage of thirteen (13) volts must be applied to a memory cell so as to program it selectively.
Therefore, there is a need for an EPROM structure that operates utilizing a voltage not much greater than 5 volts applied selectively to the individual memory cells.
SUMMARY OF THE INVENTION
Briefly, according to an aspect of the present invention, an EPROM structure includes a common gate capacitance disposed at each memory cell to raise the potential at the floating gate transistor to the level required for writing by applying to the gate capacitances a voltage, common to all the memory cells.
An advantage of this solution is that the common voltage does not need to be decoded. For this reason, high voltage transistors with other gate oxide thicknesses and diffusions are not necessary. This saves numerous mask and process steps in production, so that the electrical parameters of the standard transistors are not changed by additional process steps. On the other hand, voltages in excess of 20 volts can be present at the additional gate capacitance, since these need not be switched.
An economic advantage is that the production steps for the EPROM structure can be inserted without complication and without great expense into a conventional CMOS production process for integrated circuits.
The additional gate capacitance is preferably disposed above the floating gate of each memory cell. Furthermore, the floating gate transistor in particular is a depletion n-channel transistor, whose gate is charged negatively by hot electrons, so the floating gate transistor assumes an “off” state.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.


REFERENCES:
patent: 5212541 (1993-05-01), Bergemont
patent: 5243559 (1993-09-01), Murai
patent: 5352619 (1994-10-01), Hong
patent: 5471422 (1995-11-01), Chang et al.
patent: 5933732 (1999-08-01), Lin et al.
patent: 6025129 (2000-02-01), Nova et al.
patent: 6075293 (2000-06-01), Li et al.

Affiliated with

Also associated with

Rating

EPROM structure for a semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with EPROM structure for a semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EPROM structure for a semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3327948