EPROM programming

Details EPROM programming EPROM programming

1989-06-09

1990-12-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365104, 365185, G11C 1140

Patent

active

049775413

ABSTRACT:
An EPROM memory transistor programming arrangement is disclosed in which programming voltage for a memory transistor is applied via a load line of series connected N-channel MOS transistors which are controlled by low voltage NAND gate having low voltage address, write select and data inputs, through a high voltage inverter. The arrangement may be implemented entirely by N-channel MOS transistors which enables a compact silicon implementation and requires no separate BVDSS breakdown protection.

REFERENCES:
patent: 4761764 (1988-08-01), Watanabe
patent: 4811292 (1989-03-01), Watanabe

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