EPROM memory device having a test circuit

Static information storage and retrieval – Read/write circuit – Testing

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365230, G11C 700

Patent

active

046513043

ABSTRACT:
An EPROM memory device includes a plurality of reprogrammable memory cells arranged in the form of a matrix and a test circuit capable of having two or more memory cells selected for operation at the same time during the test mode, to thereby reduce the required testing time significantly.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4342103 (1982-07-01), Higuchi et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4603405 (1986-07-01), Michael

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