EPROM circuit with error correction

Details EPROM circuit with error correction EPROM circuit with error correction

2000-06-15

2001-03-13

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S094000, C365S103000

Reexamination Certificate

active

06201762

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an EPROM circuit with error correction.
2. Description of the Prior Art
Generally, in EPROMs (Electrically Programmable Read-Only Memory), there is a possibility of occurrence of the unintentionally erasing error due to dispersion in the data maintaining interval of each memory cell (EPROM cell) or noise. That is, bit data may changes from the logic value representing the programmed condition to the logic value representing the unprogrammed condition. Moreover, there is the unintentionally writing error wherein the logical value representing the unprogrammed condition to the unprogrammed condition, though the probability of occurrence of unintentionally writing error is lower than the unintentionally erasing error.
To prevent these errors, an EPROM circuit with correction adopting three-bit majority determination method has been proposed. Japanese patent application provisional publication No. 57-143656 discloses such a prior art EPROM circuit with correction.
FIG. 2
is a block diagram of such a prior art EPROM circuit.
The EPROM circuit of this prior art including a plurality of bit (storing) circuits having output lines, respectively, each including three EPROM cells MA, MB, and MC and a majority determining circuit for determining majority among output values of three EPROM cells MA, MB, and MC and outputting the majority result. The majority is determined such that the same value which is outputted from more than one of the EPROMs is determined as majority.
The majority determining circuit T includes three two-input NOR gates
1
to
3
and three-input NOR gate
4
of which output is connected to each of outputting lines OUT(1) to OUT(n).
In this EPROM circuit with error correction, if more than one outputs of three EPROMs MA, MB, MC are correct, the value can be judged correct.
For example, values stored in the EPROMs MA, MB, MC change from “1, 1, 1” (correct logic values) to either of “0, 1, 1”, “1, 0, 1”, or “1, 1, 0”, all inputs of the three-input NOR gate
4
remains “0”, because there is no two-input NOR gate of which both inputs are supplied with “0”. Therefore, the correct value of “1” is outputted from the three-input NOR gate
4
.
Inversely, values stored in the EPROMs MA, MB, MC change from “0, 0, 0” (correct logic values) to either of “1, 0, 0”, “0, 1, 0”, or “0, 0, 1” due to the unintentionally writing error, there is at least one of two-input NOR gate of which both inputs remains “0”, so that the two-input NOR gate still supplies “1” to the three-input NOR gate
4
. Thus, the three-input NOR gate
4
outputs correct value of “0”. In this prior art, three EPROMs were necessary for each bit.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior EPROM circuit.
According to the present invention, a first aspect of the present invention provides an EPROM circuit comprising: first and second EPROM cells, in accordance with the same one-bit data, each either being unprogrammed to output a first logic value representing an unprogrammed condition when reading or being programmed to output a second logic value representing a programmed condition when reading; and logic operation means for outputting the first logic value when both the first and second EPROM cells output the first logic value and outputting the second logic value when at least one of the first and second EPROM cells output the second logic value.
The logic operation means outputs the second logic value indicating the programmed condition with priority to the first logic value representing the unprogrammed condition. An OR gates can be used as the logic operation means if the first logic value is “0” and the second logic value is “1”. On the other hand, an AND gates can be used as the logic operation means if the first logic value is “1” and the second logic value is “0”.
According to this EPROM circuit, though an unintentional erasing error occurs in either of EPROM cells, that is, though the output of the EPROM cell changes from the second logic value to the first logic value, the correct second logic value is outputted, so that the unintentional erasing error can be corrected.
In the first aspect, it is considered that a probability of occurrence of the unintentional erasing error is higher than that of the unintentional writing error. Thus, if either of two EPROM cells outputs the second logic value indicating the programmed condition, the correct second logic value is outputted. If both EPROM cells output the first logic value (unprogrammed condition), the logic operation means outputs the first logic value.
According to the present invention, a second aspect of the present invention provides an EPROM circuit comprising: N storing circuits for storing N-bit data, each including: first and second EPROM cells, in accordance with the same one-bit data, each either being unprogrammed to output a first logic value representing an unprogrammed condition when reading or being programmed to output a second logic value representing a programmed condition when reading; and logic operation means for outputting the first logic value when both the first and second EPROM cells output the first logic value and outputting the second logic value when at least one of the first and second EPROM cells output the second logic value; inverting means for inverting an output of the logic operation means; disagreement detection means for detecting disagreement between the outputs of the first and second EPROM cells; and switching means for outputting either of outputs of logic operation means or the inverting means; parity data storing means for storing a first parity of the N-bit data; parity detecting means for detecting a second parity of N of the logic operation means; and agreement detection means for detecting agreement between the first and second parties, each of the switching circuit outputting the output of the logic gate means when the agreement detection means detects the agreement and outputting the output of the inverting means when the agreement detection means does not detect the agreement and the disagreement detection means detects the disagreement, N being a natural number.
Preferably, the parity data storing means may comprise third to fifth EPROM cells, each either being programed or being unprogrammed in accordance with the parity data. The EPROM circuit may further comprise majority detection means for detecting majority among outputs of the third to fifth EPROM cells. The agreement detection means detects the agreement with majority result as the first parity.
To correct an unintentionally writing error, first disagreement between the first parity and the second parity is detected. Moreover, second disagreement between outputs of the first and second EPROM cells is detected in the N storing circuits.
In the presence of the unintentionally writing error, the logic value of the logic operation means at the mth storing circuit changes from “0” to “1”, so that the second parity changes from the original value. Thus, the second parity disagrees with the first parity, so that a correction signal is outputted.
In the presence of the correction signal, one of the N storing circuits in which there is the second disagreement is detected. The output of the logic operation means of the detected storing circuit is inverted so that the unintentionally writing error is corrected.
The first parity is stored in another EPROM circuit including three EPROM cells storing the same parity data. A majority determining means determines majority of outputs in three EPROM cells. Each of the first and second parities indicates that the number of the logic values “1” in the N bit data or the N bit outputs of the logic operation means is even or odd.


REFERENCES:
patent: 5581501 (1996-12-01), Sansbury et al.
patent: 5742540 (1998-04-01), Wakasugi et al.
patent: 5812450 (1998-09-01), Sansbury et al.
patent: 57-143656 (1982-09-01), None
patent: 58-70497 (1983-04-01), None
patent: 62-192837 (1987-08-01), None
patent: 9-28

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