EPROM and RAM cell layout with equal pitch for use in fault tole

Details EPROM and RAM cell layout with equal pitch for use in fault tole EPROM and RAM cell layout with equal pitch for use in fault tole

1980-02-11

1983-07-12

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, 371 10, G11C 1140

Patent

active

043934749

ABSTRACT:
A fault tolerant memory device includes an array of rows and columns of dynamic random access memory cells and a set of EPROM cells of the floating gate type laid out with the same pitch, one aligned with each row, to store the identity of rows having bad cells. The EPROM cells are formed in preferred manner which permits them to be made with a standard N-channel process, and allows the row lines of the RAM and control gate connections to the EPROM cells to be of the same spacing.

REFERENCES:
patent: 3765001 (1973-10-01), Beausoleil

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