Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-04
2002-09-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S769000, C438S763000, C438S767000, C438S606000, C257S295000, C257S310000, C117S208000, C117S220000
Reexamination Certificate
active
06451711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to III-V semiconductor wafer coating and manufacturing and more specifically to surface protection of III-V compound semiconductor structures.
2. Description of the Related Art
The prior art in III-V epitaxial wafer technology employs a semiconductor layer as the top layer in a compound semiconductor epitaxial layer structure including, for example GaAs, In
1−x
Ga
x
As, In
1−y
Ga
y
P, Al
1−x
Ga
x
As, InGaAsP, InSb etc., depending on the specific device/circuit application and the particular compound semiconductor substrate. The use of a semiconducting top layers in prior epitaxial wafer technology results in a semiconductor surface structure that is easily oxidized upon exposure to the atmosphere. Since the oxidization and or contamination of the top layer of the semiconductor structure occurs immediately and uncontrollably upon exposing the compound semiconductor wafer to the oxygen, water vapor, hydrocarbons, and other chemicals in the atmosphere, the physical and electronic properties of the newly oxidized semiconductor structure are altered in an uncontrollable and unpredictable manner. After such contamination and oxidization, detrimental electrical and chemical surface properties are observed in compound semiconductor structures that have detrimental effects on electronic and optoelectronic properties that negatively effect the subsequent device and integrated circuit performance. The degree of complication and degradation of a particular device or integrated circuit is subject to the particular device/circuit processing and application. For example, the fabrication and performance of unipolar Field Effect Transistor devices/circuits may be deleteriously effected by atmospheric exposure, oxygen or water vapor exposure, or oxygen plasma exposure, that leads to Fermi level pinning, and also instability of the gate-source and gate-drain regions. Since a high quality native oxide on GaAs and other III-V semiconductors cannot be formed by processes such as thermal oxidation or surface oxidation, the fabrication of useful and stable MOSFET devices has not been possible to date in GaAs or InP based semiconductors.
Uncontrollable and detrimental electrical and surface properties are caused by chemical surface reactions resulting in the formation of native oxides and dangling bonds on compound semiconductor interfaces. The surface is also rendered thermodynamically unstable after formation of the native oxide and exhibits a pinned Fermi level. More specifically, the high GaAs surface reactivity induces Fermi level pinning and surface instability after surface exposure as small as 10
5
Langmuirs (1 Langmuir=10
−6
Torr). Surface preparation techniques conducted after exposure to air or oxygen including exposure to compounds and suspensions of sulfur and selenium, etc. have yielded compound semiconductor surfaces and interfaces that are unstable and not useful in the manufacturing of any type of GaAs integrated circuits and electronic or optoelectronic devices.
Other Prior art, U.S. Pat. No. 5,451,548, entitled “Electron Beam Deposition of Gallium Oxide Thin Films using a Single Purity Crystal Layer”, issued Sep. 19, 1995, and U.S. Pat. No. 5,550,089, entitled “Gallium Oxide Coatings for Optoelectronic Devices Using Electron Beam Evaporation of a High Purity Single Crystal Gd
3
Ga
5
O
12
Source”, issued Aug. 27, 1996, reported that thermodynamically stable, III-V semiconductor surfaces and/or interfaces with low interface state density can be fabricated when a specific insulating cap layer is deposited in-situ on GaAs based semiconductor epitaxial layers using e-beam evaporation of Gd
3
Ga
5
O
12
while maintaining ultra-high vacuum (UHV). Other prior art, such as U.S. Pat. No. 6,030,453, ‘III-V Epitaxial Wafer Production’, issued Feb. 29, 2000 reports that gallium oxide layers on GaAs may be formed using Ga
2
O
3
thermally evaporated from an oxide crucible fabricated from BeO and other oxide materials. However in our experience, the resulting films containing gallium and oxygen produced from thermal evaporation using a high temperature effusion cell from a BeO crucible are heavily doped with Be that is known to be an impurity and dopant in GaAs that results in unreliable devices and unreliable integrated circuits. Furthermore since the resulting Be concentration can exceed 10
21
cm
−3
, the resulting gallium oxide layers produced possess residual conductivity, and thus the resulting oxide films are not insulating in nature and character. A useful protective coating for GaAs must be free of impurities at concentrations below one part in 10
19
cm
−3
, and more preferably completely free of impurities at levels below 1 part in 10
16
cm
−3
. Furthermore, the resulting GaAs/coating interface must be formed at extremely low pressures to limit GaAs surface exposure to <10-100 Langmuirs of various impurities while simultaneously preserving the GaAs bulk and surface stoichiometry. The process described in both patents detailing the prior art is not useful or manufacturable because the previously disclosed processes produce coating layers that are laden with impurities that render the subsequent semiconductor devices and circuits essentially non-functional or unreliable in normal operation.
Therefore, it would be highly advantageous to provide new methods of manufacturing such compound semiconductor insulator interfaces that overcome the limitations of the prior art.
It is a purpose of the present invention to provide a new and improved III-V epitaxial wafer production process that includes the placement of a useful protective, non-contaminating and passivating coating on the compound semiconductor surface.
It is another purpose of the present invention to provide a new and improved III-V epitaxial wafer with improved stability and reliability.
It is still another purpose of the present invention to provide a new and improved III-V wafer which is relatively easy to fabricate and use for semiconductor device manufacture in both the electronic and opto-electronic fields.
BRIEF SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a method of coating, protecting, and passivating the surface of a compound semiconductor wafer structure including the steps of providing a compound semiconductor wafer structure with a surface and forming a truly insulating cap layer on the surface of a compound semiconductor wafer structure by thermally evaporating insulating material onto the wafer structure provided that such evaporation occurs on an atomically clean compound semiconductor surface, in an ultra high vacuum environment, and using a polycrystalline Ga
2
O
3
that is placed in a metallic Ir crucible that is clean, outgassed at temperatures in excess of 1700° C. in a ultra high vacuum environment and conically shaped using the electro-forming process.
In this specific semiconductor production process, a single-wafer epitaxial production system is provided including, loading, transfer, and storage modules with a III-V growth chamber attached and a second insulator deposition chamber also attached to the centralized transfer module. A compound semiconductor wafer with polished surface is placed in the loading module and the pressure therein is reduced to <10
−6
Torr. The compound semiconductor wafer is moved through the transfer module to the III-V growth chamber where the base pressure is below 10
−10
Torr and layers of compound semiconductor material are epitaxially grown on the surface of the compound semiconductor wafer. The compound semiconductor wafer is then moved to the transfer module and then immediately into the insulator chamber, while maintaining an ultra-high vacuum environment at all times. A subsequent insulating cap layer is formed by thermally evaporating Ga
2
O
3
material from an electroformed Iridium crucible onto the layer topmost of compound sem
Neifeld IP Law PC
Osemi, Incorporated
Smith Matthew
Yevsikov V.
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