Epitaxial silicon wafer and fabrication method thereof

Details Epitaxial silicon wafer and fabrication method thereof Epitaxial silicon wafer and fabrication method thereof

2011-08-02

2011-08-02

Speer, Timothy M (Department: 1784)

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Reexamination Certificate

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07989073

ABSTRACT:
An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <110 > direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100 } wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.

REFERENCES:
patent: 5877039 (1999-03-01), Tanizawa
patent: 2005/0217560 (2005-10-01), Tolchinsky et al.
patent: 2006/0068568 (2006-03-01), Yanase
patent: 2006/0131553 (2006-06-01), Yamanaka et al.
patent: 2009/0084373 (2009-04-01), Oishi
patent: 2009/0304994 (2009-12-01), Daub et al.
patent: 1498516 (2005-01-01), None
patent: 159204 (2005-11-01), None
patent: 2001-253797 (2001-09-01), None
patent: 2004-265918 (2004-09-01), None
patent: 2005-039111 (2005-10-01), None
Matsushita et al. “Precise Control of Annealed Wafer for Nanometer Devices”, High Purity Silicon 9, 210thECS meeting, vol. 4, Iss. 3, Oct. 2006, pp. 159-168.
Yoshida et al., “Preparation of the atomically straight step edge Si(111) substrates as templates for nanostructure fabrication”, Materials Research Society Symposium Proceedings. vol. 832, (2005), pp. F10.17.1-F10.17.6.
Korean Intellectual Property Office, “Notice of Preliminary Rejection” for Korean Application No. 10-2007-0089803, issued Feb. 19, 2009. This application is the Korean counterpart of U.S. Appl. No. 11/850,591.
European Search Report dated Dec. 17, 2010 in connection with corresponding European Patent Application No. 07017348.9-2203.
SEMI, “SEMI MF1241-95 (Reapproved 2000) Terminology of Silicon Technology”, 2003, pp. 1-9.
Stanley Wolf, “Silicon Processing for the VLSI Era—vol. IV”, “Chapter 2, 300-mm Silicon Wafers”, May 1, 2002, pp. 17-74.
D. Dijkkamp et al., “Scanning tunneling microscopy study of Si (001) and Si (110) surface structures resulting from different thermal cleaning treatments”, Journal of Vacuum Science & Technology, Jan./Feb. 1990, pp. 218-221.

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