Methods and apparatus for multi-modal wafer testing

Details Methods and apparatus for multi-modal wafer testing Methods and apparatus for multi-modal wafer testing

Filed on

2011-06-14

Date issued

2011-06-14

Examiner

Patel, Paresh (Department: 2829)

Patent Class

Electricity: measuring and testing

SubClass

Fault detecting in electric circuits and of electric components

SubSubClass

Of individual circuit component or element

Type

Reexamination Certificate

Status

active

Patent number

07960986

Description

ABSTRACT:
Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

REFERENCES:
patent: 4975638 (1990-12-01), Evans et al.
patent: 6181145 (2001-01-01), Tomita et al.
patent: 6297658 (2001-10-01), Nakata et al.
patent: 6991969 (2006-01-01), Johnson

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