EOS/ESD protection for high density integrated circuits

Details EOS/ESD protection for high density integrated circuits EOS/ESD protection for high density integrated circuits

1998-06-17

2000-03-21

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

H02H 900

Patent

active

060409681

ABSTRACT:
A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.

REFERENCES:
patent: 5430595 (1995-07-01), Wagner et al.
patent: 5616943 (1997-04-01), Nguyen et al.
patent: 5731941 (1998-03-01), Hargrove et al.
patent: 5740000 (1998-04-01), Stackhouse et al.
Paper: "EOS/ESD Analysis of High-Density Logic Chips," unnumbered (S. Ramaswamy, C. Duvvury, A. Amerasekera, V. Reddy and S.M. Kang), No Date.

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