Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-08-21
1996-09-17
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Testing
36518905, 36523008, G11C 1300
Patent
active
055575730
ABSTRACT:
A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. A test mode control circuit, having a first and a second test mode control input, is used, during special test operation mode, to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the array of memory cells. Contemporaneously are also exercised entire paths of buffers. The integrated circuit is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test one or more integrated circuits on the same wafer in a short time, requiring only a limited number of test signals. It is possible, indeed, to connect in parallel power supply and test inputs of a plurality of integrated circuits and test them simultaneously. For example by connecting only four probes to one of the plurality of integrated circuits (ground, supply voltage and two test mode inputs), it is possible to write all 0's or all 1's and to deselect the entire memory array simultaneously in all integrated circuits during the test. This circuit allows to use very simple test equipment and reduces dramatically test times avoiding consequent burn in of packaged devices.
REFERENCES:
patent: 4651304 (1987-03-01), Takata
patent: 5208776 (1993-05-01), Nasu et al.
patent: 5339277 (1994-08-01), McClure
patent: 5341336 (1994-08-01), McClure
patent: 5471430 (1995-11-01), Sawada
Fears Terrell W.
Jorgenson Lisa K.
SGS-Thomson Microelectronics Inc.
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