Ensuring consistency of an instruction cache with a store cache

Details Ensuring consistency of an instruction cache with a store cache Ensuring consistency of an instruction cache with a store cache

1997-06-24

2000-12-26

Kim, Kenneth S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395567, 711125, 711141, 711145, G06F 938

Patent

active

06164840&

ABSTRACT:
A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and, subsequently, executes another instruction requiring a data fetch from the same address. According to this method, a write cache prevents any addressed instruction from residing in the write cache and the instruction cache at the same time. Thus, when an instruction having a store address not already present in the write cache is retired to the write cache, the write cache instructs the instruction cache to invalidate any data stored therein having a same address. The flush instruction prevents execution of any other instructions after the store at least until the store to the memory address has been allocated to a write cache of the processor, thus enabling the write cache to invalidate the subsequent instruction at the same address in the instruction cache. The method insures instruction cache consistency without the need to check every store against the instruction cache.

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