Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2002-01-23
2004-08-17
Padmanabhan, Mano (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S052000, C710S054000, C710S059000, C711S118000, C711S208000
Reexamination Certificate
active
06779084
ABSTRACT:
BACKGROUND
This invention relates to enqueue operations for multi-buffer packets.
A network processor may store newly received data packets of varying sizes in memory buffers. For example, a network processor connected to a network using the Ethernet protocol may receive packets ranging in size from 64 bytes to 1500 bytes, whereas a network processor connected to a network using the SONET protocol may receive packets ranging from 40 bytes to 1500 bytes or, in some instances, jumbo packets of more than 9 kilobytes. To avoid the use of multiple buffers to store a packet, the buffer size may be set to the size of the largest possible packet that the system can handle. However, because some packets may be small compared to the maximum packet size, allocating a memory buffer that is the maximum packet size to store each data packet is not efficient.
REFERENCES:
patent: 5974518 (1999-10-01), Nogradi
patent: 6522188 (2003-02-01), Poole
Bernstein Debra
Rosenbluth Mark B.
Wolrich Gilbert
Namazi Mehdi
Padmanabhan Mano
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