Enlarged align tolerance in buried contact process using sidewal

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

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Details

438586, 438595, 438948, 438301, H01L 21425

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active

059239980

ABSTRACT:
A method of manufacturing a buried contact is disclosed, wherein a thin silicon oxide layer is formed on the silicon substrate. The thin oxide functions as a gate dielectric. Subsequently, a thin first polysilicon layer is formed on the thin silicon oxide layer. Then, a buried contact opening is defined by a first photoresist mask. The portion of the thin polysilicon layer exposed through the first photoresist mask and the thin silicon oxide layer underneath the exposed thin polysilicon are anisotropically etched to forma buried contact hole. An ion implantation is performed into the substrate throughout the buried contact hole to form an N+region. The first photoresist mask is removed and a layer of undoped silicon oxide is deposited on the entire surface. An anisotropic etching is used to etch the undoped silicon oxide. The etching depth can be controlled by this process. Residual amounts of undoped silicon oxide are retained on the vertical edges of the buried contact hole to act as spacers. A second layer of polysilicon is then deposited on the entire surface. A second photoresist mask is formed to define a pattern in the second polysilicon layer. Portions of the second polysilicon layer exposed through the second photoresist mask are etched using an anisotropic etching process. The high etching selectivity obtainable between the polysilicon layer and silicon oxide spacers avoids damage to the substrate in the case of a left misalignment. The alignment tolerance of the second photoresist mask is determined by the width of the silicon oxide spacer. A second implantation is then performed to form a source/drain N+region which is in contact with the previously formed N+region. Discontinuity of the two N+regions due to misalignment in the second masking step is avoided.

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Stanley Wolf, "Silicon Process for the VLSI Era", Lattice Press, Sunset Beach, California, 1986 pp. 295-308.

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