Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-02-13
2002-04-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S303000, C438S301000, C438S514000, C438S664000
Reexamination Certificate
active
06380057
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device fabrication, particularly to self-aligned silicide (salicide) technology.
BACKGROUND ART
As gate electrode lengths are scaled down, the source and drain junctions and polycrystalline silicon line width must also be scaled down. However, scaling down the source and drain junctions and polycrystalline line width increases parasitic resistance in the source and drain diffusion layers and the gate electrode, and also increases the sheet and contact resistance of the gate electrode and source/drain regions.
Salicide technology comprises forming metal silicide layers on the source/drain regions and/or on the gate electrode of a semiconductor device in a self-aligned manner. A conventional approach to reduce resistivity involves forming a multi-layered structure comprising a low resistance refractory metal silicide layer on a doped polycrystalline silicon, typically referred to as a polycide. Salicide technology reduces parasitic sheet and contact resistance in the source and drain diffusion layers and the gate electrode that results from scaling down the source and drain junctions and polycrystalline silicon line width.
Silicides are typically formed by reacting a metal with silicon (Si) within a specified temperature range for a specific period of time. Silicide layers are self-aligned. Sidewall spacers, e.g., silicon nitride or silicon dioxide, are formed on the side surfaces of the gate electrode, followed by a blanket deposition of metal and annealing to react the metal with Si in the gate electrode and the source/drain regions, while the sidewall spacers prevent reaction with Si from the side surfaces of the gate electrode.
During annealing, the wafer is heated to a reaction temperature and held at the reaction temperature for a period of time sufficient for the metal layer to react with underlying Si to form a metal silicide layer on the source/drain regions and the gate electrode. Multiple annealing steps may be employed.
Various metals react with Si to form a metal silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create metal silicides when manufacturing semiconductor devices utilizing salicide technology. However, Ti and Co silicides have certain characteristics that negatively impact semiconductor device performance.
Titanium silicide imposes high sheet resistance for lines narrower than 0.35 micrometers. For example, as TiSi
2
is formed in narrower and narrower lines, the resistance increases. Another significant limitation is that TiSi
2
initially forms a high resistivity phase (C49), and transformation from C49 to a low resistivity phase (C54) is nucleation limited, e.g., a high temperature is required to affect the phase change.
Cobalt silicide, unlike TiSi
2
, exhibits less linewidth dependence of sheet resistance. However, CoSi
2
, like TiSi
2
, still consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with Si on insulator (SIO) substrates. Without enough Si to react with Co to form CoSi
2
, a thin layer of CoSi
2
results and the silicide lacks the properties needed to ensure that the device functions properly. The thickness of the metal silicide layer is an important parameter because a thin metal silicide layer is more resistive than a thicker metal silicide layer of the same material. Therefore, thicker metal silicide layers increase semiconductor device speed, while thinner metal silicide layers reduce device speed.
Recently, attention has turned towards nickel (Ni) to form nickel silicide utilizing salicide technology. Nickel silicide avoids many limitations associated with TiSi
2
and CoSi
2
. Unlike Ti where Si diffuses into the metal layer when forming a Ti silicide, Ni, like Co, diffuses into Si, which helps to limit bridging between the metal silicide layer on the gate electrode and a metal silicide layer on the associated source/drain regions. The formation of nickel silicide requires less Si than TiSi
2
and CoSi
2
. Nickel silicide also exhibits almost no line width dependence on sheet resistance. Nickel silicide is normally annealed in a one step process, vis-à-vis a process requiring an anneal, an etch, and a second anneal, as occurs in TiSi
2
and CoSi
2
saliciding. In addition, nickel silicide exhibits lower film stress, i.e., causes less wafer distortion, than conventional Ti or Co silicides.
Although the use of Ni in salicide technology has certain advantages over using Ti or Co, there are problems associated with Ni. Metal silicide resistivity and, thus, semiconductor device performance, varies based on whether the silicide is metal-rich. Low resistivity is the preferred phase for metal suicides, including nickel silicide, as it improves device performance in the areas of switching speed and source to drain drive current. It is difficult to control nickel silicide transformation with conventional salicide technology in a manner that effects transformation to the desirable NiSi low resistivity phase from the undesirable Ni
2
Si high resistivity phase without forming rough interfaces between the nickel silicide layers and underlying Si or bridges between the nickel silicide layer on the gate electrode and a nickel silicide layers on the associated source/drain regions.
The transformation to a low resistivity nickel silicide is affected by the temperature at which annealing occurs. In order to fully convert Ni
2
Si to NiSi, annealing typically must occur at 400° C. or greater. However, the higher annealing temperatures result in rough interfaces between the nickel silicide layer and the underlying Si layer. A rough interface increases junction leakage, creates the possibility of spiking, and limits the thickness to which the silicide layer can be grown, all of which adversely affect semiconductor performance.
In addition to the problems associated with smooth interface formation, undesirable bridging is encountered at conventional annealing temperatures, particularly when silicon nitride sidewall spacers are used. Sidewall spacers typically comprise silicon dioxide or silicon nitride, but silicon nitride sidewall spacers are often preferable because silicon nitride is highly conformal and the sidewall spacers can be added and removed as needed throughout out the manufacturing process. However, at typical annealing temperatures, conductive bridges form between the nickel silicide layer on the gate electrode and the nickel silicide layers on associated source/drain regions when the heat causes nickel silicide to creep out of the active regions across the surface of the spacers. Such bridging interferes with semiconductor device performance by creating electrical shorts between different regions of the semiconductor device.
There exists a need for salicide technology that enables the formation of a low resistivity nickel silicide layer on the gate electrode and source/drain regions of a semiconductor device without the formation of rough interfaces between the nickel silicide layer and the underlying Si or bridging between the nickel silicide layer on the gate electrode and the nickel silicide layers on associated source/drain regions, particularly when using silicon nitride sidewall spacers.
DISCLOSURE OF THE INVENTION
These and other needs are met by embodiments of the present invention, which provide a method of salicide processing in semiconductor device fabrication, the method comprising forming a crystalline silicon substrate, forming a gate dielectric layer on the silicon substrate, and a gate electrode on the gate dielectric layer, forming source/drain regions, forming an oxide liner on the side surfaces of the gate electrode, forming silicon nitride sidewall spacers on the oxide liner, implanting nickel into the exposed source/drain regions to amorphize an upper portion thereof, depositing nickel over the wafer, heating the wafer to recrystallize the implanted sourc
Besser Paul R.
Buynoski Matthew S.
King Paul L.
Kluth George Jonathan
Advanced Micro Devices , Inc.
Bowers Charles
Nguyen Thanh
LandOfFree
Enhancement of nickel silicide formation by use of nickel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhancement of nickel silicide formation by use of nickel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhancement of nickel silicide formation by use of nickel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2819161