Enhancement in throughput and planarity during CMP using a diele

Details Enhancement in throughput and planarity during CMP using a diele Enhancement in throughput and planarity during CMP using a diele

1994-08-17

1996-02-27

Thomas, Tom

Fishing, trapping, and vermin destroying

437228, 437235, H01L 2144

Patent

active

054948541

ABSTRACT:
A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

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