Enhanced T-gate structure for modulation doped field effect...

Details Enhanced T-gate structure for modulation doped field effect... Enhanced T-gate structure for modulation doped field effect...

2002-07-29

2004-05-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S167000, C438S187000

Reexamination Certificate

active

06740535

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and more specifically to modulation doped field effect transistors (MODFETs) having a conductive T-shaped gate. A structure and method are disclosed which allow for higher device performance and better T-gate scalability.
BACKGROUND OF THE INVENTION
Today's integrated circuits include a vast number of transistor devices formed in a variety of semiconductor materials. Smaller devices are the key to enhanced performance and to increased reliability. As devices are scaled down, however, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next.
Modulation doped field effect transistors (MODFETs) hold promise for high frequency, low noise applications [see, for example, S. J. Koester et al., “SiGe p-MODFETs on silicon-on-sapphire substrates with 116 GHz fmax,” IEEE Electron Device Letters 22 92 (2001)]. State-of-the-art MODFETs typically increase device speed (often characterized in terms of the unity gain frequency f
t
) by shrinking the gate length to reduce carrier transit times. However, shrinking the gate dimensions also increases the gate resistance, R
G
, adversely affecting several aspects of device performance.
The requirement for a low gate resistance has led to the development of T-gates, such as T-gate
10
shown in
FIG. 1
, which, for a given gate length, reduce the values of R
G
[see, for example, U. K. Mishra et al., “Novel high performance self-aligned 0.1-mm long T-gate AlInAs—GaInAs HEMT,” IEDM Tech. Dig. 180 (1988)]. As its name suggests, the T-gate comprises a narrow neck portion (
20
in
FIG. 1
) that defines the gate length, and a wider top portion, or T-bar, (
30
in
FIG. 1
) that provides the bulk of the gate conductivity. The T-gate
10
in
FIG. 1
is a freestanding T-gate, namely it stands on a surface without any additional support. For brevity from hereon such a freestanding T-gate structure is referred to as a free T-gate.
In order to maintain a low R
G
, it is desirable to shrink only the neck portion of the T-gate while retaining a wide, upper T-bar portion. However, the top-heavy geometry of the free T-gate gives these structures an inherent mechanical instability, resulting in poor yield. In addition, the neck portion of the T-gate is also extremely vulnerable to chemical attack during subsequent processing. These yield issues, aggravated by shrinking gate lengths, impose severe limitations on the ultimate scalability and applicability of free T-gate structures for MODFET circuits. The yield problem associated with T-gates is highlighted by the fact that even though individual SiGe MODFET devices with excellent characteristics have been fabricated, there have been few demonstrations of circuits fabricated using these devices.
Some prior art T-gate schemes encapsulate a free T-gate neck in dielectric supports.
FIGS. 2A-2C
illustrate such a scheme. In U.S. Pat. No. 6,159,781 to Y. Pan et al., entitled “Way to fabricate the self-aligned T-shape gate to reduce gate resistivity,” incorporated herein by reference, describes a T-shaped opening,
12
in
FIG. 2A
, formed in dielectric layer
14
to form the structure of FIG.
2
A. Opening
12
is filled with conductive gate material
16
, to form the structure of FIG.
2
B. Then dielectric layer
14
is etched back, using the T-bar portion of the gate as a mask, to form the structure of
FIG. 2C
with dielectric supports
18
. However this patent does not teach the present invention.
Dielectric supports with the prior art geometry of
FIG. 2C
completely fill the volume under the T-bar portion overhang, a potential disadvantage if additional conductive layers are to be deposited, since conductive material may unintentionally accumulate on the exposed edges of the supports and short the source/drain regions (not shown) to the gate. In addition, the dielectric supports of the prior art are all formed from conventional dielectrics such as silicon dioxides, silicon oxynitrides, and silicon nitrides, materials with relatively high dielectric constants (k>3.5). T-gates thus formed have a relatively high-k dielectric completely underfilling the overhang of the free T-gate that results in a considerable increase in the parasitic gate capacitance associated with the fringing fields present in the dielectric surrounding the gate.
The aforementioned parasitic gate capacitance will play an increasingly important role as the gate length is shortened and will result in a significant reduction in maximum frequency of operation. Since MODFETs are primarily targeted for microwave applications any parasitic capacitances must be minimized. Likewise, interconnect RC delays must be minimized by using a low-k dielectric between any interconnect wiring.
Another important parameter affecting MODFET performance is the parasitic source resistance R
S
. A low value of R
S
is essential to improving both the noise performance and the unity power gain frequency f
max
. The T-gate is compatible with the use of a self-aligned process for forming the source/drain contacts which can help minimize R
S
by reducing the source-to-gate spacing [see, for example, S. J. Koester et al., “High-frequency noise performance of SiGe p-channel MODFETs,” Electronics Letters 36 674 (2000)]. However, the source-to-gate spacing is still limited by the width of the overhang of the T-bar portion of the T-gate. Retaining the benefits of the T-gate while further reducing the source-to-gate spacing is desirable for pushing up the high frequency performance of MODFETs.
It is therefore an object of this invention to provide an enhanced T-gate structure that (i) can be scaled to shorter gate lengths while maintaining a high yield, (ii) has a low gate parasitic capacitance, and (iii) enables the self-aligned formation of source and drain contacts, preferably with source-to-gate spacing less than the overhang width of the T-bar portion of the T-gate.
It is also an object of this invention to provide a process for fabricating an enhanced T-gate that (i) can be scaled to shorter gate lengths while maintaining a high yield, (ii) has a low gate parasitic capacitance, and (iii) enables the self-aligned formation of source and drain contacts with source-to-gate spacing preferably less than the overhang of the T-bar portion of the T-gate.
It is an additional object of this invention to provide a device structure containing an enhanced T-gate that can be scaled to shorter gate lengths while maintaining high performance and yield.
It is another object of this invention to provide a device structure containing an enhanced T-gate that enables the self-aligned formation of source and drain contacts with source-to-gate spacing preferably less than the overhang of the T-bar portion of the T-gate.
It is a yet another object of this invention to provide a scheme for fabricating circuits using a device structure containing an enhanced T-gate and having low interconnect capacitance.
SUMMARY OF THE INVENTION
In accordance with the objects listed above, the present invention describes an enhanced T-gate structure that has a thin insulating layer with a low dielectric constant disposed on the neck of the T-gate. This insulating layer provides additional mechanical support and protects the vulnerable neck of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. By using a thin conformal insulating layer with a low dielectric constant it is possible to reduce the parasitic capacitances associated with the fringing fields surrounding the gate. This insulating layer can also make it possible to reduce the source-to-gate spacing because metal can be deposited in a self-aligned manner under the overhang of the T-gate without shorting the source and gate, in contrast to the prior art supported T-gate of FIG.
2
.
The thin insulating layer with a low dielectric constant disposed on the neck of the

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