Enhanced structure of extensible time-sharing bus capable of...

Details Enhanced structure of extensible time-sharing bus capable of... Enhanced structure of extensible time-sharing bus capable of...

2007-11-06

2007-11-06

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S105000, C710S106000, C710S058000

Reexamination Certificate

active

11113039

ABSTRACT:
An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read or data write on the address and data bus, thereby reducing interface pins and obtaining flexible and multiplicative memory.

REFERENCES:
patent: 4481572 (1984-11-01), Ochsner
patent: 5499385 (1996-03-01), Farmwald et al.
patent: 5793990 (1998-08-01), Jirgal et al.
patent: 6119189 (2000-09-01), Gafken et al.
patent: 6493773 (2002-12-01), Daniel et al.
patent: 6493778 (2002-12-01), Lee et al.

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