Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-17
2001-04-17
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C257S900000
Reexamination Certificate
active
06218716
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing resistance and increasing effective polysilicon width for a narrow polysilicon line in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, a silicide is often formed on top of a polysilicon gate and overlying the source and drain regions within a substrate. Typically, a titanium layer is deposited over the wafer. The wafer is subjected to a thermal process which causes the underlying silicon to react with the titanium layer to form titanium silicide.
FIG. 16
illustrates a partially completed integrated circuit device of the prior art. A gate electrode
16
has been formed on the surface of a semiconductor substrate
10
. Source and drain regions
20
have been formed within the substrate. Sidewall spacers
18
are typically composed of silicon dioxide or silicon nitride. A layer of titanium
24
is deposited over the surface of the wafer. A rapid thermal process causes the silicon atoms within the polysilicon gate and the substrate to diffuse into the titanium layer and react with the titanium to form titanium silicide
26
, as illustrated in FIG.
17
. The titanium layer
24
over the sidewall spacers
18
and the field oxide regions
12
is not reacted and can be removed easily. However, silicon from the gate and from the substrate can diffuse into the titanium layer overlying the sidewall spacers causing titanium silicide
28
to form overlying the spacers as well. This is the so-called bridging problem. The titanium silicide layer
28
over the spacers shorts the source/drain to the gate leading to malfunction of the device.
The salicide process is used to lower resistance and therefore improve device performance and reduce chip size. However, resistance is increased dramatically for narrow polysilicon lines, such as less than 0.25 &mgr;m. This is caused by polysilicon critical dimension variation and non-uniform salicide thickness.
U.S. Pat. No. 5,648,287 to Tsai et al teaches two sets of silicon oxide spacers on the sidewalls of a gate, and a nitrogen-implanted amorphous silicon layer overlying the gate and source/drain regions. The nitrogen-rich layer acts as an oxidation barrier. U.S. Pat. No. 4,912,061 to Nasr shows a salicidation process using disposable silicon nitride spacers. U.S. Pat. No. 5,091,807 to Sanchez uses polysilicon and oxide spacers before salicidation. U.S. Pat. No. 5,658,807 to Manning teaches a method of salicidation of the sidewalls of a polysilicon gate. U.S. Pat. No. 4,716,131 to Okazawa et al teaches salicidation of the polysilicon sidewalls and source and drain regions first followed by a second salicidation of the top of the polysilicon gate.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a silicided polysilicon gate in the fabrication of an integrated circuit device.
Another object of the present invention is to provide an effective and very manufacturable method of fabricating a silicided polysilicon gate with reduced resistance in the fabrication of an integrated circuit device.
A further object of the invention is to provide a method of preventing gate to source/drain bridging in the fabrication of a silicided polysilicon gate.
A still further object is to provide a method of reducing resistance of a narrow polysilicon line in the fabrication of a silicided polysilicon gate.
Yet another object is to provide a method of increasing effective polysilicon width at a narrow polysilicon line in the fabrication of a silicided polysilicon gate.
Yet another object is to provide a method of increasing salicide thickness at a narrow polysilicon line in the fabrication of a silicided polysilicon gate.
Yet another object is to provide a method of increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate.
In accordance with the objects of this invention a method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is achieved. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate. The silicon oxide layer on top of gate electrode is removed whereby the silicon nitride spacers extend above the gate electrode. A metal silicide is formed on the top surface of the gate electrode and over the source and drain regions. The dielectric spacers extending higher than the gate electrode prevent source/drain bridging during silicidation. This completes the formation of the salicided polysilicon gate electrode.
Also in accordance with the objects of the present invention, an improved silicided polysilicon gate in an integrated circuit device is achieved. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the gate dielectric layer. First spacers made of silicon are formed at both sides of the gate dielectric layer and the gate electrode. Second spacers made of a dielectric material are formed at the outer sides of the first spacers and extending above the gate. A metal silicide layer is formed on top of the gate and between the second spacers. Implanted source and drain regions are formed in the semiconductor substrate at the outer sides of the second spacers. Metal silicide areas are formed on the source and drain regions.
REFERENCES:
patent: 4716131 (1987-12-01), Okazawa et al.
patent: 4808544 (1989-02-01), Matsui
patent: 4908326 (1990-03-01), Ma et al.
patent: 4912061 (1990-03-01), Nasr
patent: 5091763 (1992-02-01), Sanchez
patent: 5168072 (1992-12-01), Moslehi
patent: 5322809 (1994-06-01), Moslehi
patent: 5648287 (1997-07-01), Tsai et al.
patent: 5658807 (1997-08-01), Manning
patent: 5661052 (1997-08-01), Inoue et al.
patent: 5747373 (1998-05-01), Yu
patent: 5902125 (1999-05-01), Wu
patent: 6013569 (2000-01-01), Lur et al.
patent: 6031266 (2000-02-01), Honna
patent: 6074922 (2000-06-01), Wang et al.
Hsu Jung-Hsien
Wang Pi-Shan
Weng Chun-Wen
Ackerman Stephen B.
Pike Rosemary L. S.
Prenty Mark V.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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