Enhanced stress transfer in an interlayer dielectric by...

Details Enhanced stress transfer in an interlayer dielectric by... Enhanced stress transfer in an interlayer dielectric by...

2011-08-09

2011-08-09

Nguyen, Thinh T (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S695000, C438S696000, C257S327000

Reexamination Certificate

active

07994059

ABSTRACT:
By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

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Translation of Official Communication Dated Oct. 24, 2007, for serial No. 102007016897.9-33.

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